 |
CMOS 3.0 V core with versatile I/O
SPI with multi-I/O
SPI clock polarity and phase modes 0 and 3
DDR option
Extended addressing: 24- or 32-bit address options
Serial command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families
Multi I/O command set and footprint compatible with S25FL-P SPI family
READ commands
Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
AutoBoot - Power up or reset and execute a Normal or Quad read command automatically at a preselected address
Common flash interface (CFI) data for configuration information
Programming (1.5 MBps)
256- or 512-byte page programming buffer options
Quad-input page programming (QPP) for slow clock systems
Automatic ECC-internal hardware error correction code generation with single bit error correction
Erase (0.5 to 0.65 MBps)
Hybrid sector size option - Physical set of thirty two 4-KB sectors at top or bottom of address space with all remaining sectors of 64 KB, for compatibility with prior generation S25FL devices.
Uniform sector option - always erase 256-KB blocks for software compatibility with higher density and future devices.
Cycling endurance
100,000 program-erase cycles, minimum
Data retention
20 year data retention, minimum
Security features
OTP array of 1024 bytes
Block protection
Status Register bits to control protection against program or erase of a contiguous range of sectors.
Hardware and software control options
Advanced sector protection (ASP)
Individual sector protection controlled by boot code or password
65-nm MIRRORBIT™ technology with Eclipse architecture
Core supply voltage: 2.7 V to 3.6 V
I/O supply voltage: 1.65 V to 3.6 V
SO16 and FBGA packages
Datasheet | Please read the Important Notice and Warnings at the end of this document | 001-98283 Rev. *S |
page 1 | 2022-08-10 |
Logic block diagram
Temperature range/grade:
Industrial (40°C to +85°C)
Industrial Plus (40°C to +105°C)
Automotive AEC-Q100 grade 3 (40°C to +85°C)
Automotive AEC-Q100 grade 2 (40°C to +105°C)
Automotive AEC-Q100 grade 1 (40°C to +125°C)
Packages (all Pb-free)
16-lead SOIC (300 mil)
WSON 6 8 mm
- BGA-24 6 8 mm
5 5 ball (FAB024) and 4 6 ball (FAC024) footprint options
Known good die (KGD) and known tested die
Data Path
SRAM
I/O
X Decoders
CS#
SCK
MIRRORBIT™
Array
SI/IO0
SO/IO1
Y Decoders
WP#/IO2
Data Latch
Control Logic
HOLD#/IO3
RESET#
Performance summary
Table 1 Maximum read rates with the same core and I/O voltage (VIO = VCC = 2.7 V to 3.6 V)
Command | Clock rate (MHz) | MBps |
Read | 50 | 6.25 |
Fast Read | 133 | 16.6 |
Dual Read | 104 | 26 |
Quad Read | 104 | 52 |
Table 2 Maximum read rates with lower I/O voltage (VIO = 1.65 V to 2.7 V, VCC = 2.7 V to 3.6 V)
Command | Clock rate (MHz) | MBps |
Read | 50 | 6.25 |
Fast Read | 66 | 8.25 |
Dual Read | 66 | 16.5 |
Quad Read | 66 | 33 |
Table 3 Maximum read rates DDR (VIO = VCC = 3 V to 3.6 V)
Command | Clock rate (MHz) | MBps |
Fast Read DDR | 80 | 20 |
Dual Read DDR | 80 | 40 |
Quad Read DDR | 80 | 80 |
Table 4 Typical program and erase rates
Operation | KBps |
Page programming (256-byte page buffer - Hybrid sector option) | 1000 |
Page programming (512-byte page buffer - Uniform sector option) | 1500 |
4-KB physical sector erase (Hybrid sector option) | 30 |
64-KB physical sector erase (Hybrid sector option) | 500 |
256-KB logical sector erase (Uniform sector option) | 500 |
Table 5 Current consumption
Operation | Current (mA) |
Serial read 50 MHz | 16 (max) |
Serial read 133 MHz | 33 (max) |
Quad read 104 MHz | 61 (max) |
Quad DDR read 80 MHz | 90 (max) |
Program | 100 (max) |
Erase | 100 (max) |
Standby | 0.07 (typ) |
Serial peripheral interface with multiple input / output (SPI-MIO) 12
Pinouts and signal descriptions 13
Core Voltage Supply (VCC) 18
Versatile I/O Power Supply (VIO) 18
Supply and Signal Ground (VSS) 18
The Infineon S25FL128S and S25FL256S devices are flash non-volatile memory products using:
MIRRORBIT™ technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65-nm process lithography
This family of devices connect to a host system via a SPI. Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or
256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.
Executing code directly from flash memory is often called eXecute-in-Place or XIP. By using FL-S devices at the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramati- cally.
The S25FL128S and S25FL256S products offer high densities coupled with the flexibility and fast performance required by a variety of embedded applications. They are ideal for code shadowing, XIP, and data storage.
The S25FL128S and S25FL256S devices are command set and footprint compatible with prior generation FL-K and FL-P families.
Table 1 FL generations comparison[1, 2, 3, 4, 5]
Parameter | FL-K | FL-P | FL-S |
Technology node | 90 nm | 90 nm | 65 nm |
Architecture | Floating gate | MIRRORBIT™ | MIRRORBIT™ Eclipse |
Release date | In Production | In Production | 2H2011 |
Density | 4 Mb - 128 Mb | 32 Mb - 256 Mb | 128 Mb - 256 Mb |
Bus width | x1, x2, x4 | x1, x2, x4 | x1, x2, x4 |
Supply voltage | 2.7V - 3.6V | 2.7V - 3.6V | 2.7V - 3.6V / 1.65V - 3.6V VIO |
Normal read speed (SDR) | 6 MBps (50 MHz) | 5 MBps (40 MHz) | 6 MBps (50 MHz) |
Fast read speed (SDR) | 13 MBps (104 MHz) | 13 MBps (104 MHz) | 17 MBps (133 MHz) |
Dual read speed (SDR) | 26 MBps (104 MHz) | 20 MBps (80 MHz) | 26 MBps (104 MHz) |
Quad read speed (SDR) | 52 MBps (104 MHz) | 40 MBps (80 MHz) | 52 MBps (104 MHz) |
Fast read speed (DDR) | – | – | 20 MBps (80 MHz) |
Dual read speed (DDR) | – | – | 40 MBps (80 MHz) |
Notes
256B program page option only for 128-Mb and 256-Mb density FL-S devices.
FL-P column indicates FL129P MIO SPI device (for 128-Mb density).
64-KB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.
FL-K family devices can erase 4-KB sectors in groups of 32 KB or 64 KB.
See the individual datasheets for further details.
Table 1 FL generations comparison[1, 2, 3, 4, 5] (continued)
Parameter | FL-K | FL-P | FL-S |
Quad read speed (DDR) | – | – | 80 MBps (80 MHz) |
Program buffer size | 256B | 256B | 256B / 512B |
Erase sector size | 4 KB / 32 KB / 64 KB | 64 KB / 256 KB | 64 KB / 256 KB |
Parameter sector size | 4 KB | 4 KB | 4 KB (option) |
Sector erase time (typ.) | 30 ms (4 KB), 150 ms (64 KB) | 500 ms (64 KB) | 130 ms (64 KB), 520 ms (256 KB) |
Page programming time (typ.) | 700 µs (256B) | 1500 µs (256B) | 250 µs (256B), 340 µs (512B) |
OTP | 768B (3 x 256B) | 506B | 1024B |
Advanced sector protection | No | No | Yes |
Auto Boot mode | No | No | Yes |
Erase suspend/resume | Yes | No | Yes |
Program suspend/resume | Yes | No | Yes |
Operating temperature | 40°C to +85°C | 40°C to +85°C / +105°C | 40°C to +85°C / +105°C / +125°C |
Notes
256B program page option only for 128-Mb and 256-Mb density FL-S devices.
FL-P column indicates FL129P MIO SPI device (for 128-Mb density).
64-KB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.
FL-K family devices can erase 4-KB sectors in groups of 32 KB or 64 KB.
See the individual datasheets for further details.
Prior generation FL memories either do not have error status bits or do not set them if program or erase is attempted on a protected sector. The FL-S family does have error reporting status bits for program and erase operations. These can be set when there is an internal failure to program or erase or when there is an attempt to program or erase a protected sector. In either case, the program or erase operation did not complete as requested by the command.
The size and format (address map) of the OTP area is different from prior generations. The method for protecting each portion of the OTP area is different. For additional details, see “Secure silicon region (OTP)” on page 63.
The Configuration Register Freeze bit CR1[0], locks the state of the block protection bits as in prior generations. In the FL-S family, it also locks the state of the Configuration Register TBPARM bit CR1[2], TBPROT bit CR1[5], and the secure silicon region (OTP) area.
The command for erasing an 8-KB area (two 4-KB sectors) is not supported.
The command for erasing a 4-KB sector is supported only in the 128-Mb and 256-Mb density FL-S devices and only for use on the thirty two 4-KB parameter sectors at the top or bottom of the device address space.
The erase command for 64-KB sectors are supported for the 128-Mb and 256-Mb density FL-S devices when the ordering option for 4-KB parameter sectors with 64-KB uniform sectors are used. The 64-KB erase command may be applied to erase a group of sixteen 4-KB sectors.
The erase command for a 256-KB sector replaces the 64-KB erase command when the ordering option for 256-KB uniform sectors is used for the 128-Mb and 256-Mb density FL-S devices.
The deep power down (DPD) function is not supported in FL-S family devices.
The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can issue the former DPD command, to access a new bank address register. The bank address register allows SPI memory controllers that do not support more than 24 bits of address, the ability to provide higher order address bits for commands, as needed to access the larger address space of the 256-Mb density FL-S device. For additional infor- mation, see “Extended address” on page 47.
The FL-S family introduces several new features to SPI category memories:
Extended address for access to higher memory density.
AutoBoot for simpler access to boot code following power up.
Enhanced High Performance read commands using mode bits to eliminate the overhead of SIO instructions when repeating the same type of read command.
Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher clock rate read commands.
DDR read commands for SIO, DIO, and QIO.
Automatic ECC for enhanced data integrity.
Advanced sector protection for individually controlling the protection of each sector. This is very similar to the advanced sector protection feature found in several other Infineon parallel interface NOR memory families.
Serial peripheral interface with multiple input / output (SPI-MIO)
Many memory devices connect to their host system with separate parallel control, address, and data signals that require a large number of signal connections and larger package size. The large number of connections increase power consumption due to so many signals switching and the larger package increases cost.
The S25FL128S and S25FL256S devices reduce the number of signals for connection to the host system by serially transferring all control, address, and data information over 4 to 6 signals. This reduces the cost of the memory package, reduces signal switching power, and either reduces the host connection count or frees host connectors for use in providing other features.
The S25FL128S and S25FL256S devices use the industry standard single bit Serial Peripheral Interface (SPI) and also supports optional extension commands for two bit (Dual) and four bit (Quad) wide serial transfers. This multiple width interface is called SPI Multi-I/O or SPI-MIO.
CS#
VCC
SO/IO1
HOLD#/IO3
WP#/IO2
SCK
VSS
SI/IO0
Figure 2 Leadless package (WSON), top view[6]
NC NC
RESET#/ RFU
NC
DNU SCK VSS VCC NC
DNU CS# RFU WP#/IO2 NC
DNU SO/IO1 SI/IO0 HOLD#/IO3 NC
NC NC NC VIO/RFU NC
1
2
3
4
5
A
B
C
D
E
Figure 3 24-ball BGA, 5 5 ball footprint (FAB024), top view[7]
Notes
RESET# and VIO are pulled to VCC internal to the memory device.
Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use
NC
F
E
D
C
B
A
4
3
2
1
NC
NC
NC RESET#/ RFU
DNU SCK VSS VCC
DNU CS# RFU WP#/IO2
DNU SO/IO1 SI/IO0 HOLD#/IO3
NC
NC
NC VIO/RFU
NC
NC
NC
Figure 4 24-ball BGA, 4 6 ball footprint (FAC024), top view[9]
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Note
Signal connections are in the same relative positions as FAB024 BGA, allowing a single PCB footprint to use
Table 2 Signal descriptions
Signal name | Type | Description |
RESET# | Input | Hardware Reset: LOW = Device resets and returns to Standby state, ready to receive a command. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used. |
SCK | Input | Serial Clock |
CS# | Input | Chip Select |
SI / IO0 | I/O | Serial Input for single bit data commands or IO0 for Dual or Quad commands. |
SO / IO1 | I/O | Serial Output for single bit data commands. IO1 for Dual or Quad commands. |
WP# / IO2 | I/O | Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad commands. |
HOLD# / IO3 | I/O | Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad commands. |
VCC | Supply | Core Power Supply. |
VIO | Supply | Versatile I/O Power Supply. |
VSS | Supply | Ground. |
NC | Unused | Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a PCB. However, any signal connected to an NC must not have voltage levels higher than VIO. |
RFU | Reserved | Reserved for Future Use. No device internal signal is currently connected to the package connector but there is potential future use of the connector for a signal. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in compatible footprint devices. |
DNU | Reserved | Do Not Use. A device internal signal may be connected to the package connector. The connection may be used by Infineon for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do not connect any host system signal to this connection. |
Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on the SI signal. Data may be sent back to the host serially on the Serial Output (SO) signal.
Dual or Quad Output commands send information from the host to the memory only on the SI signal. Data will be returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.
Dual or Quad Input/Output (I/O) commands send information from the host to the memory as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.
The RESET# input provides a hardware method of resetting the device to Standby state, ready for receiving a command. When RESET# is driven to logic LOW (VIL) for at least a period of tRP, the device:
terminates any operation in progress,
tristates all outputs,
resets the volatile bits in the Configuration Register,
resets the volatile bits in the Status Registers,
resets the Bank Address Register to ‘0’,
loads the Program Buffer with all ones,
reloads all internal configuration information necessary to bring the device to standby mode,
and resets the internal Control Unit to Standby state.
RESET# causes the same initialization process as is performed when power comes up and requires tPU time. RESET# may be asserted LOW at any time. To ensure data integrity, any operation that was interrupted by a hardware reset should be reinitiated once the device is ready to accept a command sequence.
When RESET# is first asserted LOW, the device draws ICC1 (50 MHz value) during tPU. If RESET# continues to be held at VSS, the device draws CMOS standby current (ISB).
RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used.
The RESET# input is not available on all packages options. When not available, the RESET# input of the device is tied to the inactive state, inside the package.
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR commands, and after every edge in DDR commands.
The chip select signal indicates when a command for the device is in process and the other signals are relevant for the memory device. When the CS# signal is at the logic HIGH state, the device is not selected and all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase, or Write Registers (WRR) embedded operation is in progress, the device will be in the Standby Power mode. Driving the CS# input to logic LOW state enables the device, placing it in the Active Power mode. After Power-up, a falling edge on CS# is required prior to the start of any command.
CS# toggle with no CLK and Data is considered as non-valid. The flash should not be selected (CS# LOW with no CLK and Data) when it is not being addressed. This is considered as a spec violation and can eventually cause the device to remain in busy state (SR1 = 0x03) after an embedded operation (program/erase/etc).
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed. Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock signal.
SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
When WP# is driven LOW (VIL), during a WRR command and while the Status Register Write Disable (SRWD) bit of the Status Register is set to a ‘1’, it is not possible to write to the Status and Configuration Registers. This prevents any alteration of the Block Protect (BP2, BP1, BP0) and TBPROT bits of the Status Register. As a consequence, all the data bytes in the memory area that are protected by the Block Protect and TBPROT bits, are also hardware
protected against data modification if WP# is LOW during a WRR command.
The WP# function is not available when the Quad mode is enabled (CR[1]=1). The WP# function is replaced by IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
WP# has an internal pull-up resistor; when unconnected, WP# is at VIH and may be left unconnected in the host system if not used for Quad mode.
The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the device or stopping the serial clock.
To enter the Hold condition, the device must be selected by driving the CS# input to the logic LOW state. It is recommended that the user keep the CS# input LOW state during the entire duration of the Hold condition. This is to ensure that the state of the interface logic remains unchanged from the moment of entering the Hold condition. If the CS# input is driven to the logic HIGH state while the device is in the Hold condition, the interface logic of the device will be reset. To restart communication with the device, it is necessary to drive HOLD# to the logic HIGH state while driving the CS# signal into the logic LOW state. This prevents the device from going back into the Hold condition.
The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with SCK being at the logic LOW state. If the falling edge does not coincide with the SCK signal being at the logic LOW state, the Hold condition starts whenever the SCK signal reaches the logic LOW state. Taking the HOLD# signal to the logic LOW state does not terminate any Write, Program or Erase operation that is currently in progress.
During the Hold condition, SO is in high impedance and both the SI and SCK input are Don't Care.
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with the SCK signal being at the logic LOW state. If the rising edge does not coincide with the SCK signal being at the logic LOW state, the Hold condition ends whenever the SCK signal reaches the logic LOW state.
The HOLD# function is not available when the Quad mode is enabled (CR1[1] =1). The Hold function is replaced by IO3 for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
The HOLD# signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad mode.
B
E
E
D
D
C
C
B
CS#
SCK
HOLD#
Valid Input
Don't Care
Valid Input
Don't Care
B
Valid Input
A A
SI_or_IO_(during_input) SO_or_IO_(internal)
SO_or_IO_(external)
Hold Condition Non-standard Use
Hold Condition Standard Use
Figure 5 HOLD mode operation
VCC is the voltage source for all device internal logic. It is the single voltage used for all device internal functions including read, program, and erase. The voltage may vary from 2.7 V to 3.6 V.
The Versatile I/O (VIO) supply is the voltage source for all device input receivers and output drivers and allows the host system to set the voltage levels that the device tolerates on all inputs and drives on outputs (address, control, and IO signals). The VIO range is 1.65 V to VCC. VIO cannot be greater than VCC.
For example, a VIO of 1.65 V–3.6 V allows for I/O at the 1.8 V, 2.5 V, or 3 V levels, driving and receiving signals to and from other 1.8 V, 2.5 V or 3 V devices on the same data bus. VIO may be tied to VCC so that interface signals operate at the same voltage as the core of the device. VIO is not available in all package options, when not available the VIO supply is tied to VCC internal to the package.
During the rise of power supplies, the VIO supply voltage must remain less than or equal to the VCC supply voltage. This supply is not available in all package options. For a backward compatible with the SO16 package, the VIO supply is tied to VCC inside the package; thus, the IO will function at VCC level.
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers.
No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a PCB. However, any signal connected to an NC must not have voltage levels higher than VIO.
No device internal signal is currently connected to the package connector but is there potential future use of the connector. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in compatible footprint devices.
A device internal signal may be connected to the package connector. The connection may be used by Infineon for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections.
HOLD# WP# SI
SO
SCK
HOLD# WP# SO
SI
SCK
CS2#
CS1#
CS2#
CS1#
SPI
Bus Master
FL-S
Flash
FL-S
Flash
FL-S
Flash
FL-S
Flash
Figure 6 Bus master and memory devices on the SPI Bus - Single bit data path
HOLD#
WP# IO1
IO0 SCK
HOLD# WP#
IO1 IO0
SCK
CS2#
CS1#
CS2#
CS1#
SPI
Bus Master
FL-S
Flash
FL-S
Flash
Figure 7 Bus master and memory devices on the SPI Bus - Dual bit data path
IO3 IO2 IO1 IO0
SCK
IO3 IO2
IO1 IO0
SCK
CS2#
CS1#
CS2#
CS1#
SPI
Bus Master
Figure 8 Bus master and memory devices on the SPI Bus - Quad bit data path
The S25FL128S and S25FL256S devices can be driven by an embedded microcontroller (bus master) in either of the two following clocking modes.
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the output data is always available from the falling edge of the SCK clock signal.
The difference between the two modes is the clock polarity when the bus master is in Standby mode and not transferring any data.
SCK will stay at logic LOW state with CPOL = 0, CPHA = 0
SCK will stay at logic HIGH state with CPOL = 1, CPHA = 1
CPOL=0_CPHA=0_SCK CPOL=1_CPHA=1_SCK
CS#
SI MSb
SO
MSb
Figure 9 SPI SDR modes supported
Timing diagrams throughout the remainder of the document are generally shown as both mode ‘0’ and ‘3’ by showing SCK as both HIGH and LOW at the fall of CS#. In some cases, a timing diagram may show only mode ‘0’ with SCK LOW at the fall of CS#. In such a case, mode 3 timing simply means clock is HIGH at the fall of CS# so no SCK rising edge set up or hold time to the falling edge of CS# is needed for mode ‘3’.
SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In mode ‘0’ the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of SCK because SCK is already low at the beginning of a command.
Mode ‘0’ and mode ‘3’ are also supported for DDR commands. In DDR commands, the instruction bits are always latched on the rising edge of clock, the same as in SDR commands. However, the address and input data that follow the instruction are latched on both the rising and falling edges of SCK. The first address bit is latched on the first rising edge of SCK following the falling edge at the end of the last instruction bit. The first bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle.
Instruction
Address
Mode
Dummy / DLP
Read Data
Inst. 7
Inst. 0 A31 A30
A0 M7 M6
M0
DLP7
DLP0 D0 D1
SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the next falling edge of SCK. In mode ‘0’ the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of SCK because SCK is already low at the beginning of a command.
CPOL=0_CPHA=0_SCK CPOL=1_CPHA=1_SCK
CS#
Transfer_Phase
SI SO
Figure 10 SPI DDR modes supported
All communication between the host system and S25FL128S and S25FL256S memory devices is in the form of units called commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All instruction, address, and data information is transferred serially between the host system and memory device.
All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.
Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to the host serially on the SO signal.
Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.
Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3.
Commands are structured as follows:
Each command begins with CS# going LOW and ends with CS# returning HIGH. The memory device is selected by the host driving the Chip Select (CS#) signal low throughout a command.
The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
Each command begins with an eight bit (byte) instruction. The instruction is always presented only as a single bit serial sequence on the Serial Input (SI) signal with one bit transferred to the memory device on each SCK rising edge. The instruction selects the type of information transfer or device operation to be performed.
The instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. The instruction determines the address space used. The address may be either a 24-bit or a 32-bit byte boundary, address. The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
The width of all transfers following the instruction are determined by the instruction sent. Following transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit groups per (dual) transfer on the IO0 and IO1 signals, or they may be done in 4 bit groups per (quad) transfer on the IO0-IO3 signals. Within the dual or quad groups the least significant bit is on IO0. More significant bits are placed in significance order on each higher numbered IO signal. Single bits or parallel bit groups are transferred in most to least significant bit order.
Some instructions send an instruction modifier called mode bits, following the address, to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. The next command thus does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same command type is repeated in a sequence of commands. The mode bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host.
Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
SCK continues to toggle during any read access latency period. The latency may be ‘0’ to several SCK cycles (also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from the outputs on SCK falling edge at the end of the last read latency cycle. The first read data bits are considered transferred to the host on the following SCK rising edge. Each following transfer occurs on the next SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
If the command returns read data to the host, the device continues sending data transfers until the host takes the CS# signal HIGH. The CS# signal can be driven HIGH after any transfer in the read data sequence. This will terminate the command.
At the end of a command that does not return data, the host drives the CS# input HIGH. The CS# signal must go HIGH after the eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. That is, the CS# signal must be driven HIGH when the number of clock cycles after CS# signal was driven LOW is an exact multiple of eight cycles. If the CS# signal does not go HIGH exactly at the eight SCK cycle boundary of the instruction or write data, the command is rejected and not executed.
All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSb) first. The data bits are shifted in and out of the device MSb first. All data is transferred in byte units with the lowest address byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded operation. These are discussed in the individual command descriptions.
Depending on the command, the time for execution varies. A command to read status information from an executing command is available to determine when the command completes execution and whether the command was successful.
CS# SCK
SI SO
Phase
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Instruction
CS# SCK
SI SO
Phase
Figure 11 Standalone Instruction command
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Instruction
Input Data
CS# SCK
SI SO
Phase
Figure 12 Single Bit Wide Input command
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Instruction | Data 1 | Data 2 |
Figure 13 Single Bit Wide Output command
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 31 | 1 | 0 |
Instruction | Address | Data 1 | Data 2 |
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
CS# SCK
SI SO
Phase
CS# SCK
SI SO
Phase
0
1
2
3
4
5
6
7
Figure 14 Single Bit Wide I/O command without latency
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 31 | 1 |
0 |
Instruction | Address | Dummy Cycles | Data 1 |
IO0 IO1
Phase
6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1
7 6 5 4 3 2 1 0 31 30 29 0
CS#
SCK
Figure 15 Single Bit Wide I/O command with latency
Instruction |
Address | 6 Dummy | Data 1 | Data 2 |
1
4
0
6
5
4
3
2
1
0
31
5
7
0
4
0
4
5
5
1
5
1
6
2
1
1
2
6
0
2
6
2
6
5
0
4
1
0
4
7
CS# SCK IO0 IO1 IO2 IO3
Phase
6
2
4
5
6
7
3
7
3
7
3
7
3
7
3
Figure 16 Dual Output command
Instruction | Address | Data 1 | Data 2 | Data 3 | Data 4 | Data 5 | ... |
7
5
3
1
7
5
3
1
3
1
31
CS# SCK IO0 IO1
Phase
Figure 17 Quad Output command without latency
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 30 | 2 | 0 | 6 | 4 | 2 | 0 | 6 | 4 | 2 | 0 | |||
Instruction | Address | Dummy | Data 1 | Data 2 |
Figure 18 Dual I/O command
Instruction | Address | Mode | Dummy | D1 | D2 | D3 | D4 |
2
6
6
2
6
5
4
6
2
0
1
5
7
4
2
5
4
4
0
4
3
7
3
7
3
7
3
0
4
28
CS# SCK IO0 IO1 IO2 IO3
Phase
0
1
6
3
5
1
6
2
5
0
4
30
7
0
29
5
7
3
2
1
7
1
5
1
6
31
2
1
0
31
6
7
6
5
4
3
2
1
0
7
CS# SCK
SI SO
Phase
3
5
0
4
3
2
1
0
0
1
2
3
4
5
6
7
30
7
6
5
4
Figure 19 Quad I/O command
Instruction | Address | Mode | Dummy | Data 1 | Data 2 |
3
1
7 6 5 4 3 2
5
7
1
2
0
7 6 5 4 3 2
0
7
6
5
4
4
2
1
0
30
28
29
CS# SCK IO0 IO1
Phase
6
31
3
Figure 20 DDR Fast Read with EHPLC = 00b
1 0 | 6 | 4 | 2 | 0 | 6 |
1 0 | 7 | 5 | 3 | 1 | 7 |
Instruction | Address | Mode | Dum | DLP | Data 1 |
31
27
7
3
2
16
1
4
0
1
6
30
19
21
17
13
2
9
4
0
5
1
0
4
3
15
11
7
3
7
3
26
1
2
6
2
6
10
14
18
22
7
6
5
2
0
7
5
7
8
3
12
5
5
5
0
6
1
2
3
4
6
29
6
7
1
5
4
4
CS# SCK IO0 IO1 IO2 IO3
Phase
24
1
4
3
23
25
0
20
2
6
0
6
0
1
2
5
4
28
7
3
7
0
1
2
3
4
5
Figure 21 DDR Dual I/O Read with EHPLC = 01b and DLP
Instruction | Address | Mode | Dummy | DLP | D1 | D2 |
Figure 22 DDR Quad I/O Read
Additional sequence diagrams, specific to each command, are provided in “Commands” on page 69.
This section describes the input and output signal levels as related to the SPI interface behavior.
Table 3 Interface states summary
Interface state | VCC | VIO | RESET# | SCK | CS# | HOLD# / IO3 | WP# / IO2 | SO / IO1 | SI / IO0 |
Power-off | < VCC (low) | VCC | X | X | X | X | X | Z | X |
Low power hardware data protection | < VCC (cut-off) | VCC | X | X | X | X | X | Z | X |
Power-on (cold) reset | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | X | X | X | X | X | Z | X |
Hardware (warm) reset | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HL | X | X | X | X | Z | X |
Interface Standby | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | X | HH | X | X | Z | X |
Instruction cycle | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | HH | HV | Z | HV |
Hold cycle | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HV or HT | HL | HL | X | X | X |
Single input cycle Host to Memory transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | HH | X | Z | HV |
Single latency (dummy) cycle | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | HH | X | Z | X |
Single output cycle Memory to Host transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | HH | X | MV | X |
Dual input cycle Host to Memory transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | HH | X | HV | HV |
Dual latency (dummy) cycle | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | HH | X | X | X |
Dual output cycle Memory to Host transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | HH | X | MV | MV |
QPP address input cycle Host to Memory transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | X | X | X | HV |
Quad input cycle Host to Memory transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | HV | HV | HV | HV |
Quad latency (dummy) cycle | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | X | X | X | X |
Quad output cycle Memory to Host transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | MV | MV | MV | MV |
DDR single input cycle Host to Memory transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | X | X | X | HV |
DDR dual input cycle Host to Memory transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | X | X | HV | HV |
DDR Quad input cycle Host to Memory transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | HV | HV | HV | HV |
DDR latency (dummy) cycle | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | MV or Z | MV or Z | MV or Z | MV or Z |
DDR single output cycle Memory to Host transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | Z | Z | MV | X |
Table 3 Interface states summary (continued)
Interface state | VCC | VIO | RESET# | SCK | CS# | HOLD# / IO3 | WP# / IO2 | SO / IO1 | SI / IO0 |
DDR dual output cycle Memory to Host transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | Z | Z | MV | MV |
DDR Quad output cycle Memory to Host transfer | ≥ VCC (min) | ≥ VIO (min) ≤ VCC | HH | HT | HL | MV | MV | MV | MV |
Legend:
Z = No driver - floating signal HL = Host driving VIL
HH = Host driving VIH
HV = Either HL or HH X = HL or HH or Z
HT = Toggling between HL and HH ML = Memory driving VIL
MH = Memory driving VIH
MV = Either ML or MH
When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered-off. The device does not react to external signals, and is prevented from performing any program or erase operation.
When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range.
When the core voltage supply remains at or below the VCC (low) voltage for tPD time, then rises to VCC (Minimum) the device will begin its Power-On Reset (POR) process. POR continues until the end of tPU. During tPU, the device does not react to external input signals nor drive any outputs. Following the end of tPU, the device transitions to the Interface Standby state and can accept commands. For additional information on POR, see “Power-on (cold) reset” on page 38.
Some of the device package options provide a RESET# input. When RESET# is driven LOW for tRP time, the device starts the hardware reset process. The process continues for tRPH time. Following the end of both tRPH and the reset hold time following the rise of RESET# (tRH) the device transitions to the Interface Standby state and can accept commands. For additional information on hardware reset, see “POR followed by hardware reset” on page 38.
When CS# is HIGH, the SPI interface is in Standby state. Inputs other than RESET# are ignored. The interface waits for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes LOW to begin a new command.
While in interface Standby state, the memory device draws standby current (ISB) if no embedded algorithm is in progress. If an embedded algorithm is in progress, the related current is drawn until the end of the algorithm when the entire device returns to standby current draw.
When the host drives the MSb of an instruction and CS# goes LOW, on the next rising edge of SCK the device captures the MSb of the instruction that begins the new command. On each following rising edge of SCK, the device captures the next lower significance bit of the 8-bit instruction. The host keeps RESET# HIGH, CS# LOW, HOLD# HIGH, and drives Write Protect (WP#) signal as needed for the instruction. However, WP# is only relevant during instruction cycles of a WRR command and is otherwise ignored.
Each instruction selects the address space that is operated on and the transfer format used during the remainder of the command. The transfer format may be Single, Dual output, Quad output, Dual I/O, Quad I/O, DDR Single I/O, DDR Dual I/O, or DDR Quad I/O. The expected next interface state depends on the instruction received.
Some commands are standalone, needing no address or data transfer to or from the memory. The host returns CS# HIGH after the rising edge of SCK for the eighth bit of the instruction in such commands. The next interface state in this case is Interface Standby.
When Quad mode is not enabled (CR[1] = 0), the HOLD# / IO3 signal is used as the HOLD# input. The host keeps RESET# HIGH, HOLD# LOW, SCK may be at a valid level or continue toggling, and CS# is LOW. When HOLD# is LOW a command is paused, as though SCK were held LOW. SI / IO0 and SO / IO1 ignore the input level when acting as inputs and are high impedance when acting as outputs during Hold state. Whether these signals are input or output depends on the command and the point in the command sequence when HOLD# is asserted LOW.
When HOLD# returns HIGH, the next state is the same state the interface was in just before HOLD# was asserted LOW.
When Quad mode is enabled, the HOLD# / IO3 signal is used as IO3. During DDR commands, the HOLD# and WP# inputs are ignored.
Several commands transfer information after the instruction on the single serial input (SI) signal from host to the memory device. The dual output, and quad output commands send address to the memory using only SI but return read data using the I/O signals. The host keeps RESET# HIGH, CS# LOW, HOLD# HIGH, and drives SI as needed for the command. The memory does not drive the Serial Output (SO) signal.
The expected next interface state depends on the instruction. Some instructions continue sending address or data to the memory using additional Single Input Cycles. Others may transition to Single Latency, or directly to Single, Dual, or Quad Output.
Read commands may have ‘0’ to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# HIGH, CS# LOW, and HOLD# HIGH. The Write Protect (WP#) signal is ignored. The host may drive the SI signal during these cycles or the host may leave SI floating. The memory does not use any data driven on SI / I/O0 or other I/O signals during the latency cycles. In dual or quad read commands, the host must stop driving the I/O signals on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving I/O signals during latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory does not drive the Serial Output (SO) or I/O signals during the latency cycles.
The next interface state depends on the command structure i.e., the number of latency cycles, and whether the read is single, dual, or quad width.
Several commands transfer information back to the host on the single Serial Output (SO) signal. The host keeps RESET# HIGH, CS# LOW, and HOLD# HIGH. The Write Protect (WP#) signal is ignored. The memory ignores the Serial Input (SI) signal. The memory drives SO with data.
The next interface state continues to be Single Output Cycle until the host returns CS# to HIGH ending the command.
The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host keeps RESET# HIGH, CS# LOW, HOLD# HIGH. The Write Protect (WP#) signal is ignored. The host drives address on SI / IO0 and SO / IO1.
The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are latency cycles needed or Dual Output Cycle if no latency is required.
Read commands may have ‘0’ to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the Configuration Register (CR[7:6]). During the latency cycles, the host keeps RESET# HIGH, CS# LOW, and HOLD# HIGH. The Write Protect (WP#) signal is ignored. The host may drive the SI / IO0 and SO / IO1 signals during these cycles or the host may leave SI / IO0 and SO / IO1 floating. The memory does not use any data driven on SI / IO0 and SO / IO1 during the latency cycles. The host must stop driving SI / IO0 and SO / IO1 on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory does not drive the SI / IO0 and SO / IO1 signals during the latency cycles.
The next interface state following the last latency cycle is a Dual Output Cycle.
The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps RESET# HIGH, CS# LOW, and HOLD# HIGH. The Write Protect (WP#) signal is ignored. The memory drives data on the
SI / IO0 and SO / IO1 signals during the dual output cycles.
The next interface state continues to be Dual Output Cycle until the host returns CS# to HIGH ending the command.
The Quad Page Program and Quad Output Read commands send address to the memory only on IO0. The other IO signals are ignored because the device must be in Quad mode for these commands thus the Hold and Write Protect features are not active. The host keeps RESET# HIGH, CS# LOW, and drives IO0.
For QPP the next interface state following the delivery of address is the Quad Input Cycle.
For QOR the next interface state following address is a Quad Latency Cycle if there are latency cycles needed or Quad Output Cycle if no latency is required.
The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. The Quad Page Program command transfers four data bits to the memory in each cycle. The host keeps RESET# HIGH, CS# LOW, and drives the IO signals.
For Quad I/O Read the next interface state following the delivery of address and mode bits is a Quad Latency Cycle if there are latency cycles needed or Quad Output Cycle if no latency is required. For Quad Page Program the host returns CS# HIGH following the delivery of data to be programmed and the interface returns to standby state.
Read commands may have ‘0’ to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# HIGH, CS# LOW. The host may drive the IO signals during these cycles or the host may leave the IO floating. The memory does not use any data driven on IO during the latency cycles. The host must stop driving the IO signals on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory does not drive the IO signals during the latency cycles.
The next interface state following the last latency cycle is a Quad Output Cycle.
The Quad Output Read and Quad I/O Read return data to the host four bits in each cycle. The host keeps RESET# HIGH, and CS# LOW. The memory drives data on IO0-IO3 signals during the Quad output cycles.
The next interface state continues to be Quad Output Cycle until the host returns CS# to HIGH ending the command.
The DDR Fast Read command sends address, and mode bits to the memory only on the IO0 signal. One bit is transferred on the rising edge of SCK and one bit on the falling edge in each cycle. The host keeps RESET# HIGH, and CS# LOW. The other IO signals are ignored by the memory.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
The DDR Dual I/O Read command sends address, and mode bits to the memory only on the IO0 and IO1 signals. Two bits are transferred on the rising edge of SCK and two bits on the falling edge in each cycle. The host keeps RESET# HIGH, and CS# LOW. The IO2 and IO3 signals are ignored by the memory.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Four bits are transferred on the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET# HIGH, and CS# LOW.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
DDR Read commands may have one to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# HIGH and CS# LOW. The host may not drive the IO signals during these cycles. So that there is sufficient time for the host drivers to turn off before the memory begins to drive. This prevents driver conflict between host and memory when the signal direction changes. The memory has an option to drive all the IO signals with a Data Learning Pattern (DLP) during the last 4 latency cycles. The DLP option should not be enabled when there are fewer than five latency cycles so that there is at least one cycle of high impedance for turn around of the IO signals before the memory begins driving the DLP. When there are more than 4 cycles of latency the memory does not drive the IO signals until the last four cycles of latency.
The next interface state following the last latency cycle is a DDR Single, Dual, or Quad Output Cycle, depending on the instruction.
The DDR Fast Read command returns bits to the host only on the SO / IO1 signal. One bit is transferred on the rising edge of SCK and one bit on the falling edge in each cycle. The host keeps RESET# HIGH, and CS# LOW. The other IO signals are not driven by the memory.
The next interface state continues to be DDR Single Output Cycle until the host returns CS# to HIGH ending the command.
The DDR Dual I/O Read command returns bits to the host only on the IO0 and IO1 signals. Two bits are transferred on the rising edge of SCK and two bits on the falling edge in each cycle. The host keeps RESET# HIGH, and CS# LOW. The IO2 and IO3 signals are not driven by the memory.
The next interface state continues to be DDR Dual Output Cycle until the host returns CS# to HIGH ending the command.
The DDR Quad I/O Read command returns bits to the host on all the IO signals. Four bits are transferred on the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET# HIGH, and CS# LOW.
The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to HIGH ending the command.
The configuration register bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency code selects the number of mode bit and latency cycles for each type of instruction.
The configuration register bit 1 (CR1[1]) selects whether Quad mode is enabled to ignore HOLD# and WP# and allow Quad Page Program, Quad Output Read, and Quad I/O Read commands. Quad mode must also be selected to allow Read DDR Quad I/O commands.
Some basic protection against unintended changes to stored data are provided and controlled purely by the hardware design. These are described below.
When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off. The device does not react to external signals, and is prevented from performing any program or erase operation.
Program and erase operations continue to be prevented during the Power-on Reset (POR) because no command is accepted until the exit from POR to the Interface Standby state.
When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range.
The device verifies that all program, erase, and Write Registers (WRR) commands consist of a clock pulse count that is a multiple of eight before executing them. A command not having a multiple of 8 clock pulse count is ignored and no error status is set for the command.
Table 4 Absolute maximum ratings
Storage temperature plastic packages | –65°C to +150°C |
Ambient temperature with power applied | –65°C to +125°C |
VCC | –0.5 V to +4.0 V |
–0.5 V to +4.0 V | |
Input voltage with respect to ground (VSS)[11] | –0.5 V to +(VIO + 0.5 V) |
100 mA |
Notes
VIO must always be less than or equal VCC + 200 mV.
See “Input signal overshoot” on page 32 for allowed maximums during signal transition.
No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
Stresses above those listed under Table 4 may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the op- erational sections of this datasheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Table 5 Thermal resistance
Parameter | Description | Test condition | Device | SO3016 | FAB024 | FAC024 | WNG008 | Unit |
Theta JA | Thermal resistance (Junction to | Test conditions follow standard test | 128 | 38 | 36 | 36 | 28 | °C/W |
256 | 37 | 38 | 38 | 27 | ||||
ambient) | methods and proce- dures for measuring thermal impedance in accordance with | |||||||
Theta JB | Thermal resistance (Junction to board) | 128 | 19.7 | 19 | 19 | 7.8 | °C/W | |
256 | 18.7 | 18 | 18 | 11.7 | ||||
Theta JC | Thermal resistance (Junction to case) | EIA/JESD51. with Still Air (0 m/s). | 128 | 10.9 | 11.2 | 11.2 | 12.6 | °C/W |
256 | 9.5 | 13.7 | 13.7 | 13.1 |
Operating ranges define those limits between which the functionality of the device is guaranteed.
Some package options provide access to a separate input and output buffer power supply called VIO. Packages which do not provide the separate VIO connection, internally connect the device VIO to VCC. For these packages, the references to VIO are also references to VCC.
VCC | 2.7 V to 3.6 V |
VIO | 1.65 V to VCC +200 mV |
Table 6 Temperature ranges
Parameter | Symbol | Device | Spec | Unit | |
Min | Max | ||||
Ambient temperature | TA | Industrial (I) | –40 | +85 | °C |
Industrial Plus (V) | –40 | +105 | |||
Extended (N) | –40 | +125 | |||
Automotive, AEC-Q100 grade 3 (A) | –40 | +85 | |||
Automotive, AEC-Q100 grade 2 (B) | –40 | +105 | |||
Automotive AEC-Q100 grade 1 (M) | –40 | +125 | |||
Note
Industrial Plus operating and performance parameters will be determined by device characterization and may vary from standard industrial temperature range devices as currently shown in this specification.
During DC conditions, input or I/O signals should remain equal to or between VSS and VIO. During voltage transi- tions, inputs or I/Os may overshoot VSS to –2.0V or overshoot to VIO +2.0V, for periods up to 20 ns.
20 ns
- 2.0 V
VIL
20 ns
20 ns
Figure 23 Maximum negative overshoot waveform
20 ns
20 ns
VIH
VIO + 2.0 V
20 ns
Figure 24 Maximum positive overshoot waveform
The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on VCC) until VCC reaches the correct value as follows:
VCC (min) at power-up, and then for a further delay of tPU
VSS at power-down
A simple pull-up resistor (generally of the order of 100 k) on Chip Select (CS#) can usually be used to insure safe and proper power-up and power-down.
The device ignores all instructions until a time delay of tPU has elapsed after the moment that VCC rises above the minimum VCC threshold. See Figure 25. However, correct operation of the device is not guaranteed if VCC returns below VCC (min) during tPU. No command should be sent to the device until the end of tPU.
After power-up (tPU), the device is in Standby mode (not Deep Power Down mode), draws CMOS standby current (ISB), and the WEL bit is reset.
During power-down or voltage drops below VCC (cut-off), the voltage must drop below VCC (low) for a period of tPD for the part to initialize correctly on power-up. See Figure 26. If during a voltage drop the VCC stays above VCC (cut-off) the part will stay initialized and will work correctly when VCC is again above VCC (min). In the event Power-on Reset (POR) did not complete correctly after power up, the assertion of the RESET# signal or receiving a software reset command (RESET) will restart the POR process.
Normal precautions must be taken for supply rail decoupling to stabilize the VCC supply at the device. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package supply connection (this capacitor is generally of the order of 0.1 µf).
Table 7 Power-up / power-down voltage and timing
Symbol | Parameter | Min | Max | Unit |
VCC (min) | VCC (Minimum operation voltage) | 2.7 | – | V |
VCC (cut-off) | VCC (Cut-off where re-initialization is needed) | 2.4 | – | V |
VCC (low) | VCC (Low voltage for initialization to occur) VCC (Low voltage for initialization to occur at embedded) | 1.6 2.3 | – | V |
tPU | VCC (min) to read operation | – | 300 | µs |
tPD | VCC (low) time | 15.0 | – | µs |
Time
Full Device Access
tPU
(min)
CC
V
VCC
VCC(max)
Figure 25 Power-up
Device Access Allowed
Time
tPD
(low)
CC
V
VCC
VCC(max)
(cut-off)
CC
V
tPU
(min)
CC
V
No Device Access Allowed
Figure 26 Power-down and voltage drop
Applicable within operating ranges.
Table 8 DC Characteristics — Operating temperature range –40°C to +85°C
Symbol | Parameter | Test conditions | Min | Max | Unit | |
VIL | Input low voltage | –0.5 | – | 0.2 x VIO | V | |
VIH | Input high voltage | 0.7 VIO | – | VIO+0.4 | V | |
VOL | Output low voltage | IOL = 1.6 mA, VCC = VCC min | – | – | 0.15 VIO | V |
VOH | Output high voltage | IOH = –0.1 mA | 0.85 VIO | – | V | |
ILI | Input leakage current | VCC = VCC Max, VIN = VIH or VIL | – | – | ±2 | µA |
ILO | Output leakage current | VCC = VCC Max, VIN = VIH or VIL | – | – | ±2 | µA |
ICC1 | Active power supply current (READ) | Serial SDR@50 MHz Serial SDR@133 MHz Quad SDR@80 MHz Quad SDR@104 MHz Quad DDR@66 MHz Quad DDR@80 MHz | – | – | 16 33 50 61 75 90 | mA |
ICC2 | Active power supply current (Page program) | CS# = VIO | – | – | 100 | mA |
ICC3 | Active power supply current (WRR) | CS# = VIO | – | – | 100 | mA |
ICC4 | Active power supply current (SE) | CS# = VIO | – | – | 100 | mA |
Notes
Typical values are at TAI = 25°C and VCC = VIO = 3 V.
Output switching current is not included.
Table 8 DC Characteristics — Operating temperature range –40°C to +85°C (continued)
Symbol | Parameter | Test conditions | Min | Typ[15] | Max | Unit |
ICC5 | Active power supply current (BE) | CS# = VIO | – | – | 100 | mA |
ISB (Industrial) | Standby current | RESET#, CS# = VIO; SI, SCK = VIO or VSS, Industrial temperature | – | 70 | 100 | µA |
Notes
Typical values are at TAI = 25°C and VCC = VIO = 3 V.
Output switching current is not included.
Table 9 DC characteristics — Operating temperature range -40°C to +105°C and -40°C to +125°C
Symbol | Parameter | Test Conditions | Min | Max | Unit | |
VIL | Input low voltage | –0.5 | – | 0.2 x VIO | V | |
VIH | Input high voltage | 0.7 VIO | – | VIO+0.4 | V | |
VOL | Output low voltage | IOL = 1.6 mA, VCC = VCC min | – | 0.15 x VIO | V | |
VOH | Output high voltage | IOH = –0.1 mA | 0.85 VIO | – | V | |
ILI | Input leakage current | VCC = VCC Max, VIN = VIH or VIL | – | – | ±2 | µA |
ILO | Output leakage current | VCC = VCC Max, VIN = VIH or VIL | – | – | ±2 | µA |
ICC1 | Active power supply current (READ) | Serial SDR@50 MHz Serial SDR@133 MHz Quad SDR@80 MHz Quad SDR@104 MHz Quad DDR@66 MHz Quad DDR@80 MHz | – | – | 22 35 50 61 75 90 | mA |
ICC2 | Active power supply current (Page program) | CS# = VIO | – | – | 100 | mA |
ICC3 | Active power supply current (WRR) | CS# = VIO | – | – | 100 | mA |
ICC4 | Active power supply current (SE) | CS# = VIO | – | – | 100 | mA |
ICC5 | Active power supply current (BE) | CS# = VIO | – | – | 100 | mA |
ISB | Standby current | RESET#, CS# = VIO; SI, SCK = VIO or VSS | – | 70 | 300 | µA |
Notes
Typical values are at TAI = 25°C and VCC = VIO = 3 V.
Output switching current is not included.
The device is enabled and in the Active Power mode when Chip Select (CS#) is LOW. When CS# is HIGH, the device is disabled, but may still be in an Active Power mode until all program, erase, and write operations have completed. The device then goes into the Standby Power mode, and power consumption drops to ISB.
Figure 27 Waveform element meanings
IO
0.15 x V
0.2 x VIO
- 0.5V
Timing Reference Level
0.5 x VIO
IO
0.85 x V
VIO + 0.4V
0.7 x VIO
Output Levels
Input Levels
Figure 28 Input, output, and timing reference levels
Device
Under Test
CL
Figure 29 Test setup
Table 10 AC measurement conditions
Symbol | Parameter | Min | Max | Unit |
CL | Load capacitance | 30 | pF | |
Input rise and fall times | – | 2.4 | ns | |
Input pulse voltage | 0.2 x VIO to 0.8 VIO | V | ||
Input timing ref voltage | 0.5 VIO | V | ||
Output timing ref voltage | 0.5 VIO | V | ||
Notes
Output High-Z is defined as the point where data is no longer driven.
Input slew rate: 1.5 V/ns.
AC characteristics tables assume clock and data signals have the same slew rate (slope).
DDR operation.
For more information on capacitance, please contact the IBIS models.
The device executes a Power-On Reset (POR) process until a time delay of tPU has elapsed after the moment that VCC rises above the minimum VCC threshold. See Figure 25, Table 7, and Table 12. The device must not be selected (CS# to go HIGH with VIO) during power-up (tPU), i.e. no commands may be sent to the device until the end of tPU. RESET# is ignored during POR. If RESET# is LOW during POR and remains low through and beyond the end of tPU, CS# must remain HIGH until tRH after RESET# returns HIGH. RESET# must return HIGH for greater than tRS before returning low to initiate a hardware reset.
CS# must be high at tPU end
CS#
tRH
If RESET# is low at tPU end
RESET#
tPU
VCC
VIO
Figure 30 Reset LOW at the end of POR
CS# may stay high or go low at tPU end
CS#
tPU
If RESET# is high at tPU end
RESET#
tPU
VCC
VIO
Figure 31 Reset HIGH at the end of POR
CS#
tPU
RESET#
tRS
tPU
VCC
VIO
Figure 32 POR followed by hardware reset
When the RESET# input transitions from VIH to VIL the device will reset register states in the same manner as power-on reset but, does not go through the full reset process that is performed during POR. The hardware reset process requires a period of tRPH to complete. If the POR process did not complete correctly for any reason during power-up (tPU), RESET# going LOW will initiate the full POR process instead of the hardware reset process and will require tPU to complete the POR process.
The RESET# input provides a hardware method of resetting the flash memory device to standby state.
RESET# must be HIGH for tRS following tPU or tRPH, before going low again to initiate a hardware reset.
When RESET# is driven low for at least a minimum period of time (tRP), the device terminates any operation in progress, tri-states all outputs, and ignores all read/write commands for the duration of tRPH. The device resets the interface to standby state.
If CS# is LOW at the time RESET# is asserted, CS# must return HIGH during tRPH before it can be asserted low again after tRH.
Hardware Reset is only offered in 16-lead SOIC and BGA packages.
CS#
tRPH
tRS
tRPH
tRH
tRH
Any prior reset
RESET#
tRP
Figure 33 Hardware reset
Table 12 Hardware reset parameters[24, 25]
Parameter | Description | Limit | Time | Unit |
tRS | Reset setup - Prior reset end and RESET# HIGH before RESET# LOW | Min | 50 | ns |
tRPH | Reset pulse hold - RESET# LOW to CS# LOW | Min | 35 | µs |
tRP | RESET# pulse width | Min | 200 | ns |
tRH | Reset hold - RESET# HIGH before CS# LOW | Min | 50 | ns |
Notes
RESET# LOW is optional and ignored during power-up (tPU). If Reset# is asserted LOW during the end of tPU, the device will remain in the reset state and tRH will determine when CS# may go LOW.
Sum of tRP and tRH must be equal to or greater than tRPH.
Table 13 AC characteristics (Single die package, VIO = VCC 2.7 V to 3.6 V)
Symbol | Parameter | Min | Typ | Max | Unit |
FSCK, R | SCK clock frequency for READ and 4READ instructions | DC | – | 50 | MHz |
FSCK, C | SCK clock frequency for single commands as shown in Table 48[29] | DC | – | 133 | MHz |
FSCK, C | SCK clock frequency for the following dual and Quad commands: DOR, 4DOR, QOR, 4QOR, DIOR, 4DIOR, QIOR, 4QIOR | DC | – | 104 | MHz |
FSCK, QPP | SCK clock frequency for the QPP, 4QPP commands | DC | – | 80 | MHz |
PSCK | SCK clock period | 1/ FSCK | – | | |
tWH, tCH | 45% PSCK | – | – | ns | |
tWL, tCL | 45% PSCK | – | – | ns | |
tCRT, tCLCH | Clock rise time (slew rate) | 0.1 | – | – | V/ns |
tCFT, tCHCL | Clock fall time (slew rate) | 0.1 | – | – | V/ns |
tCS | CS# high time (Read instructions) CS# high time (Program/erase) | 10 50 | – | – | ns |
tCSS | CS# active setup time (relative to SCK) | 3 | – | – | ns |
tCSH | CS# active hold time (relative to SCK) | 3 | – | – | ns |
tSU | Data in setup time | 1.5 | – | ns | |
tHD | Data in hold time | 2 | – | – | ns |
tV | Clock low to output valid | – | – | 8.0[27] 6.5[29] | ns |
tHO | Output hold time | 2 | – | ns | |
tDIS | Output disable time | 0 | – | 8 | ns |
tWPS | WP# setup time | – | – | ns | |
tWPH | WP# hold time | 100[26] | – | – | ns |
tHLCH | HOLD# active setup time (relative to SCK) | 3 | – | – | ns |
tCHHH | HOLD# active hold time (relative to SCK) | 3 | – | – | ns |
tHHCH | HOLD# non active setup time (relative to SCK) | 3 | – | – | ns |
tCHHL | HOLD# non active hold time (relative to SCK) | 3 | – | – | ns |
tHZ | HOLD# enable to output Invalid | – | – | 8 | ns |
tLZ | HOLD# disable to output Valid | – | – | 8 | ns |
Notes
Only applicable as a constraint for WRR instruction when SRWD is set to a ‘1’.
Full VCC range (2.7–3.6 V) and CL = 30 pF.
Regulated VCC range (3.0–3.6 V) and CL = 30 pF.
Regulated VCC range (3.0–3.6 V) and CL = 15 pF.
±10% duty cycle is supported for frequencies 50MHz.
Maximum value only applies during Program/Erase Suspend/Resume commands.
Table 14 AC characteristics (Single die package, VIO 1.65 V to 2.7 V, VCC 2.7 V to 3.6 V)
Symbol | Parameter | Min | Typ | Max | Unit |
FSCK, R | SCK clock frequency for READ, 4READ instructions | DC | – | 50 | MHz |
FSCK, C | DC | – | 66 | MHz | |
PSCK | SCK clock period | 1/ FSCK | – | | |
tWH, tCH | 45% PSCK | – | – | ns | |
tWL, tCL | 45% PSCK | – | – | ns | |
tCRT, tCLCH | Clock rise time (slew rate) | 0.1 | – | – | V/ns |
tCFT, tCHCL | Clock fall time (slew rate) | 0.1 | – | – | V/ns |
tCS | CS# high time (Read instructions) CS# high time (Program/erase) | 10 50 | – | – | ns |
tCSS | CS# active setup time (relative to SCK) | 10 | – | – | ns |
tCSH | CS# active hold time (relative to SCK) | 3 | – | – | ns |
tSU | Data in setup time | 5 | – | 3000[36] | ns |
tHD | Data in hold time | 4 | – | – | ns |
tV | Clock low to output valid | – | – | 14.5[33] 12.0[34] | ns |
tHO | Output hold time | 2 | – | ns | |
tDIS | Output disable time | 0 | – | 14 | ns |
tWPS | WP# setup time | 20[32] | – | – | ns |
tWPH | WP# hold time | 100[32] | – | – | ns |
tHLCH | HOLD# active setup time (relative to SCK) | 5 | – | – | ns |
tCHHH | HOLD# active hold time (relative to SCK) | 5 | – | – | ns |
tHHCH | HOLD# non active setup time (relative to SCK) | 5 | – | – | ns |
tCHHL | HOLD# non active hold time (relative to SCK) | 5 | – | – | ns |
tHZ | HOLD# enable to output invalid | – | – | 14 | ns |
tLZ | HOLD# disable to output valid | – | – | 14 | ns |
Notes
Only applicable as a constraint for WRR instruction when SRWD is set to a ‘1’.
CL = 30 pF.
CL = 15 pF.
±10% duty cycle is supported for frequencies 50 MHz.
Maximum value only applies during Program/Erase Suspend/Resume commands.
tCFT
tCRT
VIH min
VIO / 2
VIL max
tCL
tCH
PSCK
Figure 34 Clock timing
LSb IN
tHD
MSb IN
SI
SO
tSU
SCK
tCSS
tCSS
tCSH
tCSH
CS#
tCS
Figure 35 SPI single bit input timing
LSb OUT
MSb OUT
SO
tDIS
tV
tHO
tLZ
CS# SCK
SI
tCS
Figure 36 SPI single bit output timing
tV
LSB OUT
MSB OUT .
LSB IN .
MSB IN
IO
tDIS
tCS
tHO
tLZ
tHD
tSU
SCK
tCSS
tCSH
tCSS
CS#
Figure 37 SPI SDR MIO timing
tLZ
D E
C
tHZ
tLZ
B
B
A
SO_or_IO_(during_output)
tHZ
SI_or_IO_(during_input)
Hold Condition Non-standard Use
Hold Condition Standard Use
HOLD#
tHHCH tHLCH tHHCH
tCHHH tCHHL tCHHH
tHLCH
tCHHL
CS#
SCK
CS#
WP# SCK
SI SO
Phase
Figure 38 Hold timing
tWPS
tWPH
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WRR Instruction
Input Data
Figure 39 WP# input timing
Table 15 AC characteristics — DDR operation
Symbol | Parameter | 66 MHz | 80 MHz | Unit | ||||
Min | Typ | Max | Min | Typ | Max | |||
FSCK, R | SCK clock frequency for DDR READ instruction | DC | – | 66 | DC | – | 80 | MHz |
PSCK, R | SCK clock period for DDR READ instruction | 15 | – | | 12.5 | – | | ns |
tWH, tCH | Clock high time | 45% PSCK | – | – | 45% PSCK | – | – | ns |
tWL, tCL | Clock low time | 45% PSCK | – | – | 45% PSCK | – | – | ns |
tCS | CS# high time (Read instructions) | 10 | – | – | 10 | – | – | ns |
tCSS | CS# active setup time (relative to SCK) | 3 | – | – | 3 | – | – | ns |
tCSH | CS# active hold time (relative to SCK) | 3 | – | – | 3 | – | – | ns |
tSU | IO in setup time | 2 | – | 1.5 | – | ns | ||
tHD | IO in hold time | 2 | – | – | 1.5 | – | – | ns |
tV | Clock low to output valid | – | – | – | – | 6.5[37] | ns | |
tHO | Output hold time | 1.5 | – | 1.5 | – | – | ns | |
tDIS | Output disable time | – | – | 8 | – | – | 8 | ns |
tLZ | Clock to output low impedance | 0 | – | 8 | 0 | – | 8 | ns |
tO_SKEW | First output to last output data valid time | – | – | 600 | – | – | 600 | ps |
Notes
Regulated VCC range (3.0–3.6 V) and CL = 15 pF.
Maximum value only applies during Program/Erase Suspend/Resume commands.
tCS | ||||||
CS# tCSH tCSH tCSS tCSS SCK tHD tSU tHD tSU SI_or_IO MSb IN LSb IN SO | ||||||
Figure 40 SPI DDR input timing
LSb
MSb
SO_or_IO
tDIS
tV
tV
tHO
tLZ
CS# SCK
SI
tCS
Figure 41 SPI DDR output timing
pSCK
tCL
tCH
SCK
tIO_SKEW
tV
tOTT
IO Slow
Slow D1
.
Slow D2
tV
IO Fast
Fast D2
V_min
tHO
IO_valid
tDV
D1
D2
t
Fast D1
Figure 42 SPI DDR data valid window
The minimum data valid window (tDV) and tV minimum can be calculated as follows: tDV[42] = Minimum half clock cycle time (tCLH)[39] - tOTT[41] - tIO_SKEW[40]
tV _min = tHO + tIO_SKEW + tOTT
Example:
80 MHz clock frequency = 12.5 ns clock period, DDR operations and duty cycle of 45% or higher tCLH = 0.45 x PSCK = 0.45 x 12.5 ns = 5.625 ns
Bus impedance of 45 ohm and capacitance of 22 pf, with timing reference of 0.75 VCC, the rise time from ‘0’ to ‘1’ or fall time ‘1’ to ‘0’ is 1.4[44] x RC time constant (Tau)[43] = 1.4 x 0.99 ns = 1.39 ns
tOTT = rise time or fall time = 1.39 ns.
Data Valid Window
tDV = tCLH - tIO_SKEW - tOTT = 5.625 ns - 600 ps - 1.39 ns = 3.635 ns
tV Minimum
tV _min = tHO + tIO_SKEW + tOTT = 1.0 ns + 600 ps + 1.39 ns = 2.99 ns
Notes
tCLH is the shorter duration of tCL or tCH.
tIO_SKEW is the maximum difference (delta) between the minimum and maximum tV (output valid) across all IO signals.
tOTT is the maximum Output Transition Time from one valid data value to the next valid data value on each IO. tOTT is dependent on system level considerations including:
Memory device output impedance (drive strength).
System level parasitics on the IOs (primarily bus capacitance).
Host memory controller input VIH and VIL levels at which ‘0’ to 1 and 1 to ‘0’ transitions are recognized.
tOTT is not a specification tested by Infineon, it is system dependent and must be derived by the system designer based on the above considerations.
tDV is the data valid window.
Tau = R (Output Impedance) x C (Load capacitance).
Multiplier of Tau time for voltage to rise to 75% of VCC.
The S25FL128S and S25FL256S devices support 32-bit addresses to enable higher density devices than allowed by previous generation (legacy) SPI devices that supported only 24-bit addresses. A 24-bit byte resolution address can access only 16 MB (128 Mb) of maximum density. A 32-bit byte resolution address allows direct addressing of up to a 4 GB (32 Gb) of address space.
Legacy commands continue to support 24-bit addresses for backward software compatibility. Extended 32-bit addresses are enabled in three ways:
Bank address register — a software (command) loadable internal register that supplies the high order bits of address when legacy 24-bit addresses are in use.
Extended address mode — a bank address register bit that changes all legacy commands to expect 32-bits of address supplied from the host system.
New commands — that perform both legacy and new functions, which expect 32-bit address.
The default condition at power-up and after reset, is the Bank address register loaded with zeros and the extended address mode set for 24-bit addresses. This enables legacy software compatible access to the first 128 Mb of a device.
The S25FL128S device supports the extended address features in the same way but in essence ignores bits 31 to 24 of any address because the main flash array only needs 24 bits of address. This enables simple migration from the 128-Mb density to higher density devices without changing the address handling aspects of software.
Many commands operate on the main flash memory array. Some commands operate on address spaces separate from the main flash array. Each separate address space uses the full 32-bit address but may only define a small portion of the available address space.
The main flash array is divided into erase units called sectors. The sectors are organized either as a hybrid combi- nation of 4-KB and 64-KB sectors, or as uniform 256-KB sectors. The sector organization depends on the device model selected, see “Ordering information” on page 154.
Table 16 S25FL256S sector and memory address map, bottom 4-KB sectors
Sector size (KB) | Sector count | Sector range | Address range (Byte address) | Notes |
4 | 32 | SA00 | 00000000h-00000FF Fh | Sector starting address — |
: | : | |||
Sector ending address | ||||
SA31 | 0001F000h-0001FFF Fh | |||
64 | 510 | SA32 | 00020000h-0002FFF Fh | |
: | : | |||
SA541 | 01FF0000h-01FFFFF Fh |
Table 17 S25FL256S sector and memory address map, top 4-KB sectors
Sector size (KB) | Sector count | Sector range | Address range (Byte address) | Notes |
64 | 510 | SA00 | 0000000h-000FFFFh | Sector starting address — |
: | : | |||
Sector ending address | ||||
SA509 | 01FD0000h-01FDFFF Fh | |||
4 | 32 | SA510 | 01FE0000h-01FE0FF Fh | |
: | : | |||
SA541 | 01FFF000h-01FFFFF Fh |
Table 18 S25FL256S sector and memory address map, uniform 256-KB sectors
Sector size (KB) | Sector count | Sector range | Address range (8-bit) | Notes |
256 | 128 | SA00 | 0000000h-003FFFFh | Sector starting address |
: | : | |||
— Sector ending | ||||
SA127 | 1FC0000h-1FFFFFFh | |||
address |
Table 19 S25FL128S sector and memory address map, bottom 4-KB sectors
Sector size (KB) | Sector count | Sector range | Address range (Byte address) | Notes |
4 | 32 | SA00 | 00000000h-00000FF Fh | Sector starting address — |
: | : | |||
Sector ending address | ||||
SA31 | 0001F000h-0001FFF Fh | |||
64 | 254 | SA32 | 00020000h-0002FFF Fh | |
: | : | |||
SA285 | 00FF0000h-00FFFFF Fh |
Table 20 S25FL128S sector and memory address map, top 4-KB sectors
Sector size (KB) | Sector count | Sector range | Address range (Byte address) | Notes |
64 | 254 | SA00 | 0000000h-000FFFFh | Sector starting address |
: | : | |||
— Sector ending address | ||||
SA253 | 00FD0000h-00FDFFF Fh | |||
4 | 32 | SA254 | 00FE0000h-00FE0FF Fh | |
: | : | |||
SA285 | 00FFF000h-00FFFFF Fh |
Table 21 S25FL128S sector and memory address map, uniform 256-KB sectors
Sector size (KB) | Sector count | Sector range | Address range (Byte address) | Notes |
256 | 64 | SA00 | 0000000h-003FFFFh | Sector starting address |
: | : | |||
— Sector ending | ||||
SA63 | 0FC0000h-0FFFFFFh | |||
address |
Note: These are condensed tables that use a couple of sectors as references. here are address ranges that are not explicitly listed. All 256 KB sectors have the pattern XXX0000h-XXXFFFFh.
The RDID command (9Fh) reads information from a separate flash memory address space for device identifi- cation (ID) and Common Flash Interface (CFI) information. See “Device ID and common flash interface (ID-CFI) address map” on page 129 for the tables defining the contents of the ID-CFI address space. The ID-CFI address space is programmed by Infineon and read-only for the host system.
Each S25FL128S and S25FL256S memory device has a 1024-byte One Time Program (OTP) address space that is separate from the main flash array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.
In the 32-byte region starting at address ‘0’:
The 16 lowest address bytes are programmed by Infineon with a 128-bit random number. Only Infineon is able to program these bytes.
The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to permanently protect each
region from programming. The bytes are erased when shipped from Infineon. After an OTP region is programmed, it can be locked to prevent further programming, by programming the related protection bit in the OTP Lock Bytes.
The next higher 12-bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU bytes may be programmed by the host system but it must be understood that a future device may use those bits for protection of a larger OTP space. The bytes are erased when shipped from Infineon.
The remaining regions are erased when shipped from Infineon, and are available for programming of additional permanent data.
See Figure 43 for a pictorial representation of the OTP memory space.
The OTP memory space is intended for increased system security. OTP values, such as the random number programmed by Infineon, can be used to “mate” a flash component with the system CPU/ASIC to prevent device substitution.
When programmed to ‘0’ each lock bit protects its related 32-byte region from any further programming
...
Contents of Region 0 {
Reserved
Lock Bytes 16-byte Random Number
Lock Bits 31 to 0
Byte 1F
Byte 10
Byte 0
The configuration register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming when set to ‘1’. This allows trusted boot code to control programming of OTP regions then set the FREEZE bit to prevent further OTP memory space programming during the remainder of normal power-on system operation.
32-byte OTP Region 31 |
32-byte OTP Region 30 |
32-byte OTP Region 29 |
. . . |
32-byte OTP Region 3 |
32-byte OTP Region 2 |
32-byte OTP Region 1 |
32-byte OTP Region 0 |
Table 22 OTP address map
Region | Byte address range (Hex) | Contents | Initial delivery state (Hex) |
Region 0 | 000 | Least significant byte of Infineon programmed random number | Infineon programmed random number |
... | ... | ||
00F | Most significant byte of Infineon programmed random number | ||
010 to 013 | Region locking bits Byte 10 [bit 0] locks region 0 from programming when = 0 ... Byte 13 [bit 7] locks region 31 from programming when = 0 | All bytes = FF | |
014 to 01F | Reserved for Future Use (RFU) | All bytes = FF | |
Region 1 | 020 to 03F | Available for user programming | All bytes = FF |
Region 2 | 040 to 05F | Available for user programming | All bytes = FF |
... | ... | Available for user programming | All bytes = FF |
Region 31 | 3E0 to 3FF | Available for user programming | All bytes = FF |
Registers are small groups of memory cells used to configure how the S25FL-S memory device operates or to report the status of device operations. The registers are accessed by specific commands. The commands (and hexadecimal instruction codes) used for each register are noted in each register description. The individual register bits may be volatile, non-volatile, or One Time Programmable (OTP). The type for each bit is noted in each register description. The default state shown for each bit refers to the state after power-on reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the default state is the value of the bit when the device is shipped from Infineon. Non-volatile bits have the same cycling (erase and program) endurance as the main flash array.
Table 23 Register descriptions
Register | Abbreviation | Type | Bit location |
Status Register 1 | SR1[7:0] | Volatile | 7:0 |
Configuration Register 1 | CR1[7:0] | Volatile | 7:0 |
Status Register 2 | SR2[7:0] | RFU | 7:0 |
AutoBoot Register | ABRD[31:0] | Non-volatile | 31:0 |
Bank Address Register | BRAC[7:0] | Volatile | 7:0 |
ECC Status Register | ECCSR[7:0] | Volatile | 7:0 |
ASP Register | ASPR[15:1] | OTP | 15:1 |
ASP Register | ASPR[0] | RFU | 0 |
Password Register | PASS[63:0] | Non-volatile OTP | 63:0 |
PPB Lock Register | PPBL[7:1] | Volatile | 7:1 |
PPB Lock Register | PPBL[0] | Volatile Read only | 0 |
PPB Access Register | PPBAR[7:0] | Non-volatile | 7:0 |
DYB Access Register | DYBAR[7:0] | Volatile | 7:0 |
SPI DDR Data Learning Registers | NVDLR[7:0] | Non-volatile | 7:0 |
SPI DDR Data Learning Registers | VDLR[7:0] | Volatile | 7:0 |
Related commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN 06h), Write Disable (WRDI 04h), Clear Status Register (CLSR 30h).
Table 24 Status Register 1 (SR1)
Bits | Field name | Function | Type | Default state | Description |
7 | SRWD | Status Register Write Disable | Non-Volatile | 0 | 1 = Locks state of SRWD, BP, and configuration register bits when WP# is LOW by ignoring WRR command 0 = No protection, even when WP# is LOW |
6 | P_ERR | Programmin g Error Occurred | Volatile, Read only | 0 | 1 = Error occurred. 0 = No error |
5 | E_ERR | Erase Error Occurred | Volatile, Read only | 0 | 1 = Error occurred 0 = No error |
Table 24 Status Register 1 (SR1) (continued)
Bits | Field name | Function | Type | Default state | Description |
4 | BP2 | Block Protection | Volatile if CR1[3] = 1, Non-Volatile if CR1[3] = 0 | 1 if CR1[3] = 1, 0 when shipped from Infineon | Protects selected range of sectors (Block) from Program or Erase |
3 | BP1 | ||||
2 | BP0 | ||||
1 | WEL | Write Enable Latch | Volatile | 0 | 1 = Device accepts Write Registers (WRR), program or erase commands 0 = Device ignores Write Registers (WRR), program or erase commands This bit is not affected by WRR, only WREN and WRDI commands affect this bit |
0 | WIP | Write in Progress | Volatile, Read only | 0 | 1 = Device Busy, a Write Registers (WRR), program, erase or other operation is in progress 0 = Ready Device is in standby mode and can accept commands |
The Status Register contains both status and control bits:
Status Register Write Disable (SRWD) SR1[7]: Places the device in the Hardware Protected mode when this bit is set to ‘1’ and the WP# input is driven low. In this mode, the SRWD, BP2, BP1, and BP0 bits of the Status Register become read-only bits and the Write Registers (WRR) command is no longer accepted for execution. If WP# is HIGH the SRWD bit and BP bits may be changed by the WRR command. If SRWD is 0, WP# has no effect and the SRWD bit and BP bits may be changed by the WRR command. The SRWD bit has the same non-volatile endurance as the main flash array.
Program Error (P_ERR) SR1[6]: The Program Error Bit is used as a program operation success or failure indication. When the Program Error bit is set to a ‘1’ it indicates that there was an error in the last program operation. This bit will also be set when the user attempts to program within a protected main memory sector or locked OTP region. When the Program Error bit is set to a ‘1’ this bit can be reset to ‘0’ with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected by the WRR command.
Erase Error (E_ERR) SR1[5]: The Erase Error Bit is used as an Erase operation success or failure indication. When the Erase Error bit is set to a ‘1’ it indicates that there was an error in the last erase operation. This bit will also be set when the user attempts to erase an individual protected main memory sector. The Bulk Erase command will not set E_ERR if a protected sector is found during the command execution. When the Erase Error bit is set to a ‘1’ this bit can be reset to ‘0’ with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected by the WRR command.
Block Protection (BP2, BP1, BP0) SR1[4:2]: These bits define the main flash array area to be software-protected against program and erase commands. The BP bits are either volatile or non-volatile, depending on the state of the BP non-volatile bit (BPNV) in the configuration register. When one or more of the BP bits is set to 1, the relevant memory area is protected against program and erase. The Bulk Erase (BE) command can be executed only when the BP bits are cleared to 0’s. See “Block protection” on page 64 for a description of how the BP bit values select the memory array area protected. The BP bits have the same non-volatile endurance as the main flash array.
Write Enable Latch (WEL) SR1[1]: The WEL bit must be set to ‘1’ to enable program, write, or erase operations as a means to provide protection against inadvertent changes to memory or register values. The Write Enable (WREN) command execution sets the Write Enable Latch to a ‘1’ to allow any program, erase, or write commands to execute afterwards. The Write Disable (WRDI) command can be used to set the Write Enable Latch to a ‘0’ to prevent all program, erase, and write commands from execution. The WEL bit is cleared to ‘0’ at the end of any successful program, write, or erase operation. Following a failed operation, the WEL bit may remain set and should be cleared with a WRDI command following a CLSR command. After a power down/power up sequence, hardware reset, or software reset, the Write Enable Latch is set to a ‘0’ The WRR command does not affect this bit.
Write In Progress (WIP) SR1[0]: Indicates whether the device is performing a program, write, erase operation, or any other operation, during which a new operation command will be ignored. When the bit is set to a ‘1’ the device is busy performing an operation. While WIP is 1, only Read Status (RDSR1 or RDSR2), Erase Suspend (ERSP), Program Suspend (PGSP), Clear Status Register (CLSR), and Software Reset (RESET) commands may be accepted. ERSP and PGSP will only be accepted if memory array erase or program operations are in progress. The status register E_ERR and P_ERR bits are updated while WIP = 1. When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains busy and unable to receive new operation commands. A Clear Status Register (CLSR) command must be received to return the device to standby mode. When the WIP bit is cleared to ‘0’ no operation is in progress. This is a read-only bit.
Related commands: Read Configuration Register (RDCR 35h), Write Registers (WRR 01h). The Configuration Register bits can be changed using the WRR command with sixteen input cycles.
The Configuration Register controls certain interface and data protection functions.
Table 25 Configuration Register 1(CR1)
Bits | Fieldname | Function | Type | Default state | Description |
7 | LC1 | Latency code | Non-volatile | 0 | Selects number of initial read latency cycles, see latency code tables (Table 26 through Table 29) |
6 | LC0 | 0 | |||
5 | TBPROT | Configures start of block protection | OTP | 0 | 1 = BP starts at bottom (Low address) 0 = BP starts at top (High address) |
4 | DNU | DNU | OTP | 0 | Do Not Use |
3 | BPNV | Configures BP2-0 in Status Register | OTP | 0 | 1 = Volatile 0 = Non-volatile |
2 | TBPARM | Configures parameter sectors location | OTP | 0 | 1 = 4-KB physical sectors at top, (high address) 0 = 4-KB physical sectors at bottom (low address) RFU in uniform sector devices |
1 | QUAD | Puts the device into Quad I/O operation | Non-volatile | 0 | 1 = Quad 0 = Dual or Serial |
0 | FREEZE | Lock current state of BP2-0 bits in Status Register, TBPROT and TBPARM in Configuration Register, and OTP regions | Volatile | 0 | 1 = Block protection and OTP locked 0 = Block protection and OTP un-locked |
Latency Code (LC) CR1[7:6]: The Latency Code selects the number of mode and dummy cycles between the end of address and the start of read data output for all read commands.
Some read commands send mode bits following the address to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. The next command thus does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same command type is repeated in a sequence of commands.
Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array before data can be returned to the host system. Some read commands require additional latency cycles as the SCK frequency is increased.
Table 26 through Table 29 provide different latency settings that are configured by Infineon. The High Perfor- mance versus the Enhanced High Performance settings are selected by the ordering part number.
Where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not supported at the frequency shown. Read is supported only up to 50 MHz but the same latency value is assigned in each latency code and the command may be used when the device is operated at 50 MHz with any latency code setting. Similarly, only the Fast Read command is supported up to 133 MHz but the same 10b latency code is used for Fast Read up to 133 MHz and for the other dual and quad read commands up to 104 MHz. It is not necessary to change the latency code from a higher to a lower frequency when operating at lower frequencies where a particular command is supported. The latency code values for a higher frequency can be used for accesses at lower frequencies.
The High Performance settings provide latency options that are the same or faster than alternate source SPI memories. These settings provide mode bits only for the Quad I/O Read command.
The Enhanced High Performance settings similarly provide latency options the same or faster than additional alternate source SPI memories and adds mode bits for the Dual I/O Read, DDR Fast Read, and DDR Dual I/O Read commands.
Read DDR Data Learning Pattern (DLP) bits may be placed within the dummy cycles immediately before the start of read data, if there are 5 or more dummy cycles. See “Read memory array commands” on page 89 for more information on the DLP.
Table 26 Latency codes for SDR high performance
Freq. (MHz) | LC | Read | Fast Read | Read Dual Out | Read Quad Out | Dual I/O Read | Quad I/O Read | ||||||
(03h, 13h) | (0Bh, 0Ch) | (3Bh, 3Ch) | (6Bh, 6Ch) | (BBh, BCh) | (EBh, ECh) | ||||||||
Mode | Dummy | Mode | Dummy | Mode | Dummy | Mode | Dummy | Mode | Dummy | Mode | Dummy | ||
≤ 50 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 2 | 1 |
≤ 80 | 00 | – | – | 0 | 8 | 0 | 8 | 0 | 8 | 0 | 4 | 2 | 4 |
≤ 90 | 01 | – | – | 0 | 8 | 0 | 8 | 0 | 8 | 0 | 5 | 2 | 4 |
≤104 | 10 | – | – | 0 | 8 | 0 | 8 | 0 | 8 | 0 | 6 | 2 | 5 |
≤133 | 10 | – | – | 0 | 8 | – | – | – | – | – | – | – | – |
Table 27 Latency codes for DDR high performance[45]
Freq. (MHz) | LC | DDR Fast Read | DDR Dual I/O Read | Read DDR Quad I/O | |||
(0Dh, 0Eh) | (BDh, BEh) | (EDh, EEh) | |||||
Mode | Dummy | Mode | Dummy | Mode | Dummy | ||
≤ 50 | 11 | 0 | 4 | 0 | 4 | 1 | 3 |
≤ 66 | 00 | 0 | 5 | 0 | 6 | 1 | 6 |
≤ 66 | 01 | 0 | 6 | 0 | 7 | 1 | 7 |
≤ 66 | 10 | 0 | 7 | 0 | 8 | 1 | 8 |
Note
When using DDR I/O commands with the Data Learning Pattern (DLP) enabled, a Latency Code that provides 5 or more dummy cycles should be selected to allow 1 cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP. It is recommended to use LC 10 for DDR Fast Read, LC 01 for DDR Dual IO Read, and LC 00 for DDR Quad IO Read, if the Data Learning Pattern (DLP) for DDR is used.
Table 28 Latency codes for SDR enhanced high performance
Freq. (MHz) | LC | Read | Fast Read | Read Dual Out | Read Quad Out | Dual I/O Read | Quad I/O Read | ||||||
(03h, 13h) | (0Bh, 0Ch) | (3Bh, 3Ch) | (6Bh, 6Ch) | (BBh, BCh) | (EBh, ECh) | ||||||||
Mode | Dummy | Mode | Dummy | Mode | Dummy | Mode | Dummy | Mode | Dummy | Mode | Dummy | ||
≤ 50 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 2 | 1 |
≤ 80 | 00 | – | – | 0 | 8 | 0 | 8 | 0 | 8 | 4 | 0 | 2 | 4 |
≤ 90 | 01 | – | – | 0 | 8 | 0 | 8 | 0 | 8 | 4 | 1 | 2 | 4 |
≤104 | 10 | – | – | 0 | 8 | 0 | 8 | 0 | 8 | 4 | 2 | 2 | 5 |
≤133 | 10 | – | – | 0 | 8 | – | – | – | – | – | – | – | – |
Table 29 Latency codes for DDR enhanced high performance[46]
Freq. (MHz) | LC | DDR Fast Read | DDR Dual I/O Read | Read DDR Quad I/O | |||
(0Dh, 0Eh) | (BDh, BEh) | (EDh, EEh) | |||||
Mode | Dummy | Mode | Dummy | Mode | Dummy | ||
≤ 50 | 11 | 4 | 1 | 2 | 2 | 1 | 3 |
≤ 66 | 00 | 4 | 2 | 2 | 4 | 1 | 6 |
≤ 66 | 01 | 4 | 4 | 2 | 5 | 1 | 7 |
≤ 66 | 10 | 4 | 5 | 2 | 6 | 1 | 8 |
≤ 80 | 00 | 4 | 2 | 2 | 4 | 1 | 6 |
≤ 80 | 01 | 4 | 4 | 2 | 5 | 1 | 7 |
≤ 80 | 10 | 4 | 5 | 2 | 6 | 1 | 8 |
Note
When using DDR I/O commands with the Data Learning Pattern (DLP) enabled, a Latency Code that provides 5 or more dummy cycles should be selected to allow 1 cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP. It is recommended to use LC 10 for DDR Fast Read, LC 01 for DDR Dual IO Read, and LC 00 for DDR Quad IO Read, if the Data Learning Pattern (DLP) for DDR is used.
Top or Bottom Protection (TBPROT) CR1[5]: This bit defines the operation of the Block Protection bits BP2, BP1, and BP0 in the Status Register. As described in the status register section, the BP2-0 bits allow the user to optionally protect a portion of the array, ranging from 1/64, 1/4, 1/2, etc., up to the entire array. When TBPROT is set to a ‘0’ the Block Protection is defined to start from the top (maximum address) of the array. When TBPROT is set to a ‘1’ the Block Protection is defined to start from the bottom (‘0’ address) of the array. The TBPROT bit is OTP and set to a ‘0’ when shipped from Infineon. If TBPROT is programmed to 1, an attempt to change it back to ‘0’ will fail and set the Program Error bit (P_ERR in SR1[6]).
The desired state of TBPROT must be selected during the initial configuration of the device during system manufacture; before the first program or erase operation on the main flash array. TBPROT must not be programmed after programming or erasing is done in the main flash array.
CR1[4]: Reserved for Future Use
Block Protection Non-Volatile (BPNV) CR1[3]: The BPNV bit defines whether or not the BP2-0 bits in the Status Register are volatile or non-volatile. The BPNV bit is OTP and cleared to a ‘0’ with the BP bits cleared to 000 when shipped from Infineon. When BPNV is set to a ‘0’ the BP2-0 bits in the Status Register are non-volatile. When BPNV is set to a ‘1’ the BP2-0 bits in the Status Register are volatile and will be reset to binary ‘111’ after POR, hardware reset, or command reset. If BPNV is programmed to ‘1’, an attempt to change it back to ‘0’ will fail and set the Program Error bit (P_ERR in SR1[6]).
TBPARM CR1[2]: TBPARM defines the logical location of the parameter block. The parameter block consists of thirty-two 4-KB small sectors (SMS), which replace two 64-KB sectors. When TBPARM is set to a ‘1’ the parameter block is in the top of the memory array address space. When TBPARM is set to a ‘0’ the parameter block is at the Bottom of the array. TBPARM is OTP and set to a ‘0’ when it ships from Infineon. If TBPARM is programmed to 1, an attempt to change it back to ‘0’ will fail and set the Program Error bit (P_ERR in SR1[6]).
The desired state of TBPARM must be selected during the initial configuration of the device during system manufacture; before the first program or erase operation on the main flash array. TBPARM must not be programmed after programming or erasing is done in the main flash array.
TBPROT can be set or cleared independent of the TBPARM bit. Therefore, the user can elect to store parameter information from the bottom of the array and protect boot code starting at the top of the array, and vice versa. Or the user can select to store and protect the parameter information starting from the top or bottom together.
When the memory array is logically configured as uniform 256-KB sectors, the TBPARM bit is Reserved for Future Use (RFU) and has no effect because all sectors are uniform size.
Quad Data Width (QUAD) CR1[1]: When set to 1, this bit switches the data width of the device to 4 bit - Quad mode. That is, WP# becomes IO2 and HOLD# becomes IO3. The WP# and HOLD# inputs are not monitored for their normal functions and are internally set to HIGH (inactive). The commands for Serial, Dual Output, and Dual I/O Read still function normally but, there is no need to drive WP# and Hold# inputs for those commands when switching between commands using different data path widths. The QUAD bit must be set to one when using Read Quad Out, Quad I/O Read, Read DDR Quad I/O, and Quad Page Program commands. The QUAD bit is
non-volatile.
Freeze Protection (FREEZE) CR1[0]: The Freeze Bit, when set to 1, locks the current state of the BP2-0 bits in Status Register, the TBPROT and TBPARM bits in the Configuration Register, and the OTP address space. This prevents writing, programming, or erasing these areas. As long as the FREEZE bit remains cleared to logic ‘0’ the other bits of the Configuration Register, including FREEZE, are writable, and the OTP address space is program- mable. Once the FREEZE bit has been written to a logic ‘1’ it can only be cleared to a logic ‘0’ by a power-off to power-on cycle or a hardware reset. Software reset will not affect the state of the FREEZE bit. The FREEZE bit is volatile and the default state of FREEZE after power-on is ‘0’. The FREEZE bit can be set in parallel with updating other values in CR1 by a single WRR command.
Related commands: Read Status Register 2 (RDSR2 07h).
Table 30 Status Register 2 (SR2)
Bits | Field name | Function | Type | Default state | Description |
7 | RFU | Reserved | – | 0 | Reserved for Future Use |
6 | RFU | Reserved | – | 0 | Reserved for Future Use |
5 | RFU | Reserved | – | 0 | Reserved for Future Use |
4 | RFU | Reserved | – | 0 | Reserved for Future Use |
3 | RFU | Reserved | – | 0 | Reserved for Future Use |
2 | RFU | Reserved | – | 0 | Reserved for Future Use |
1 | ES | Erase Suspend | Volatile, Read only | 0 | 1 = In erase suspend mode 0 = Not in erase suspend mode |
0 | PS | Program Suspend | Volatile, Read only | 0 | 1 = In program suspend mode 0 = Not in program suspend mode |
Erase Suspend (ES) SR2[1]: The Erase Suspend bit is used to determine when the device is in Erase Suspend mode. This is a status bit that cannot be written. When Erase Suspend bit is set to 1, the device is in erase suspend mode. When Erase Suspend bit is cleared to 0, the device is not in erase suspend mode. See the Erase Suspend and Resume Commands (75h) (7Ah) for details about the Erase Suspend/Resume commands.
Program Suspend (PS) SR2[0]: The Program Suspend bit is used to determine when the device is in Program Suspend mode. This is a status bit that cannot be written. When Program Suspend bit is set to 1, the device is in program suspend mode. When the Program Suspend bit is cleared to 0, the device is not in program suspend mode. See “Program Suspend (PGSP 85h) and Resume (PGRS 8Ah)” on page 111 for details.
Related commands: AutoBoot Read (ABRD 14h) and AutoBoot Write (ABWR 15h).
The AutoBoot Register provides a means to automatically read boot code as part of the power-on reset, hardware reset, or software reset process.
Table 31 AutoBoot Register
Bits | Field name | Function | Type | Default state | Description |
31 to 9 | ABSA | AutoBoot Start Address | Non-volatile | 000000h | 512 byte boundary address for the start of boot code access |
8 to 1 | ABSD | AutoBoot Start Delay | Non-volatile | 00h | Number of initial delay cycles between CS# going LOW and the first bit of boot code being trans- ferred |
0 | ABE | AutoBoot Enable | Non-volatile | 0 | 1 = AutoBoot is enabled 0 = AutoBoot is not enabled |
Related commands: Bank Register Access (BRAC B9h), Write Register (WRR 01h), Bank Register Read (BRRD 16h) and Bank Register Write (BRWR 17h).
The Bank Address register supplies additional high order bits of the main flash array byte boundary address for legacy commands that supply only the low order 24 bits of address. The Bank Address is used as the high bits of address (above A23) for all 3-byte address commands when EXTADD = 0. The Bank Address is not used when EXTADD = 1 and traditional 3-byte address commands are instead required to provide all four bytes of address.
Table 32 Bank Address Register (BAR)
Bits | Field name | Function | Type | Default state | Description |
7 | EXTADD | Extended Address Enable | Volatile | 0b | 1 = 4-byte (32-bits) addressing required from command. 0 = 3-byte (24-bits) addressing from command + Bank Address |
6 to 1 | RFU | Reserved | Volatile | 00000b | Reserved for Future Use |
0 | BA24 | Bank Address | Volatile | 0 | A24 for 256-Mb device, RFU for lower density device |
Extended Address (EXTADD) BAR[7]: EXTADD controls the address field size for legacy SPI commands. By default (power up reset, hardware reset, and software reset), it is cleared to ‘0’ for 3-bytes (24-bits) of address. When set to ‘1’, the legacy commands will require 4 bytes (32 bits) for the address field. This is a volatile bit.
Related commands: ECC Read (ECCRD 18h). ECCSR does not have user programmable non-volatile bits. All defined bits are volatile read only status. The default state of these bits are set by hardware. See “Automatic ECC” on page 106.
The status of ECC in each ECC unit is provided by the 8-bit ECC Status Register (ECCSR). The ECC Register Read command is written followed by an ECC unit address. The contents of the status register then indicates, for the selected ECC unit, whether there is an error in the ECC unit eight bit error correction code, the ECC unit of 16 Bytes of data, or that ECC is disabled for that ECC unit.
Table 33 ECC Status Register (ECCSR)
Bits | Field name | Function | Type | Default state | Description |
7 to 3 | RFU | Reserved | 0 | Reserved for Future Use | |
2 | EECC | Error in ECC | Volatile, Read only | 0 | 1 = Single Bit Error found in the ECC unit eight bit error correction code 0 = No error. |
1 | EECCD | Error in ECC unit data | Volatile, Read only | 0 | 1 = Single Bit Error corrected in ECC unit data. 0 = No error. |
0 | ECCDI | ECC Disabled | Volatile, Read only | 0 | 1 = ECC is disabled in the selected ECC unit. 0 = ECC is enabled in the selected ECC unit. |
ECCSR[2] = 1 indicates an error was corrected in the ECC. ECCSR[1] = 1 indicates an error was corrected in the ECC unit data. ECCSR[0] = 1 indicates the ECC is disabled. The default state of “0” for all these bits indicates no failures and ECC is enabled.
ECCSR[7:3] are reserved. These have undefined high or low values that can change from one ECC status read to another. These bits should be treated as “don’t care” and ignored by any software reading status.
Related commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh).
The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced Sector Protection (ASP) features.
Table 34 ASP Register (ASPR)
Bits | Field name | Function | Type | Default state | Description |
15 to 9 | RFU | Reserved | OTP | 1 | Reserved for Future Use |
8 | RFU | Reserved | OTP | Reserved for Future Use | |
7 | RFU | Reserved | OTP | Reserved for Future Use | |
6 | RFU | Reserved | OTP | 1 | Reserved for Future Use |
5 | RFU | Reserved | OTP | Reserved for Future Use | |
4 | RFU | Reserved | OTP | Reserved for Future Use | |
3 | RFU | Reserved | OTP | Reserved for Future Use | |
2 | PWDMLB | Password Protection Mode Lock Bit | OTP | 1 | 0 = Password Protection Mode permanently enabled. 1 = Password Protection Mode not permanently enabled. |
Note
Table 34 ASP Register (ASPR) (continued)
Bits | Field name | Function | Type | Default state | Description |
1 | PSTMLB | Persistent Protection Mode Lock Bit | OTP | 1 | 0 = Persistent Protection Mode permanently enabled. 1 = Persistent Protection Mode not permanently enabled. |
0 | RFU | Reserved | OTP | 1 | Reserved for Future Use |
Note
Default value depends on ordering part number, see “Initial delivery state” on page 148.
Reserved for Future Use (RFU) ASPR[15:3, 0].
Password Protection Mode Lock Bit (PWDMLB) ASPR[2]: When programmed to 0, the Password Protection Mode is permanently selected.
Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]: When programmed to 0, the Persistent Protection Mode is permanently selected. PWDMLB and PSTMLB are mutually exclusive, only one may be programmed to ‘0’.
Related commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h).
Table 35 Password Register (PASS)
Bits | Field name | Function | Type | Default state | Description |
63 to 0 | PWD | Hidden Password | OTP | FFFFFFFF- FFFFFFFFh | Non-volatile OTP storage of 64 bit password. The password is no longer readable after the password protection mode is selected by programming ASP register bit ‘2’ to ‘0’. |
Related commands: PPB Lock Read (PLBRD A7h, PLBWR A6h).
Table 36 PPB Lock Register (PPBL)
Bits | Field name | Function | Type | Default state | Description |
7 to 1 | RFU | Reserved | Volatile | 00h | Reserved for Future Use |
0 | PPBLOCK | Protect PPB Array | Volatile | Persistent Protection mode = 1 Password Protection mode = 0 | 0 = PPB array protected until next power cycle or hardware reset 1 = PPB array may be programmed or erased. |
Related commands: PPB Read (PPBRD E2h)
Table 37 PPB Access Register (PPBAR)
Bits | Field name | Function | Type | Default state | Description |
7 to 0 | PPB | Read or Program per sector PPB | Non-volatile | FFh | 00h = PPB for the sector addressed by the PPBRD or PPBP command is programmed to 0, protecting that sector from program or erase operations. FFh = PPB for the sector addressed by the PPBRD or PPBP command is erased to 1, not protecting that sector from program or erase operations. |
Related commands: DYB Read (DYBRD E0h) and DYB Program (DYBP E1h).
Table 38 DYB Access Register (DYBAR)
Bits | Field name | Function | Type | Default state | Description |
7 to 0 | DYB | Read or Write per sector DYB | Volatile | FFh | 00h = DYB for the sector addressed by the DYBRD or DYBP command is cleared to 0, protecting that sector from program or erase operations. FFh = DYB for the sector addressed by the DYBRD or DYBP command is set to 1, not protecting that sector from program or erase operations. |
Related commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern Read (DLPRD 41h).
The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as an 8-bit Volatile Data Learning Register (VDLR). When shipped from Infineon, the NVDLR value is 00h. Once programmed, the NVDLR cannot be reprogrammed or erased; a copy of the data pattern in the NVDLR will also be written to the VDLR. The VDLR can be written to at any time, but on reset or power cycles the data pattern will revert back to what is in the NVDLR. During the learning phase described in the SPI DDR modes, the DLP will come from the VDLR. Each IO will output the same DLP value for every clock edge. For example, if the DLP is 34h (or binary 00110100) then during the first clock edge all IO’s will output 0; subsequently, the 2nd clock edge all I/O’s will output 0, the 3rd will output 1, etc.
When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR commands.
Table 39 Non-Volatile Data Learning Register (NVDLR)
Bits | Field name | Function | Type | Default state | Description |
7 to 0 | NVDLP | Non-Volatile Data Learning Pattern | OTP | 00h | OTP value that may be transferred to the host during DDR read command latency (dummy) cycles to provide a training pattern to help the host more accurately center the data capture point in the received data bits. |
Table 40 Volatile Data Learning Register (NVDLR)
Bits | Field name | Function | Type | Default state | Description |
7 to 0 | VDLP | Volatile Data Learning Pattern | Volatile | Takes the value of NVDLR during POR or Reset | Volatile copy of the NVDLP used to enable and deliver the Data Learning Pattern (DLP) to the outputs. The VDLP may be changed by the host during system operation. |
Embedded algorithm performance tables
Table 41 Program and Erase performance
Symbol | Parameter | Min | Typ[48] | Unit | |
tW | WRR Write Time | – | 140 | 500 | ms |
tPP | Page Programming (512 bytes) Page Programming (256 bytes) | – | 340 250 | 750 750[50] | µs |
tSE | Sector Erase Time (64-KB / 4-KB physical sectors) | – | 130 | 650[51] | ms |
Sector Erase Time (64 KB Top/Bottom: logical sector = 16 x 4-KB physical sectors) | – | 2,080 | 10,400 | ms | |
Sector Erase Time (256-KB logical sectors = 4 x 64-KB physical sectors) | – | 520 | 2600 | ms | |
tBE tBE | Bulk Erase Time (S25FL128S) | – | 33 | 165 | sec |
Bulk Erase Time (S25FL256S) | – | 66 | 330 | sec |
Notes
Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V; 10,000 cycles; checker- board data pattern.
Maximum value also applies to OTPP, PPBP, ASPP, and PASSP programming commands.
Maximum value also applies to the PPBE erase command.
Table 42 Program Suspend AC parameters
Parameter | Min | Typical | Max | Unit | Comments |
Program Suspend Latency (tPSL) | – | – | 40 | µs | The time from Program Suspend command until the WIP bit is 0 |
Program Resume to next Program Suspend (tPRS) | 0.06 | 100 | – | µs | Minimum is the time needed to issue the next Program Suspend command but ≥ typical periods are needed for Program to progress to completion |
Table 43 Erase Suspend AC parameters
Parameter | Min | Typical | Max | Unit | Comments |
Erase Suspend Latency (tESL) | – | – | 45 | µs | The time from Erase Suspend command until the WIP bit is 0 |
Erase Resume to next Erase Suspend (tERS) | 0.06 | 100 | – | µs | Minimum is the time needed to issue the next Erase Suspend command but ≥ typical periods are needed for the Erase to progress to completion |
The device has a 1024-byte One Time Program (OTP) address space that is separate from the main flash array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.
The OTP memory space is intended for increased system security. OTP values can “mate” a flash component with the system CPU/ASIC to prevent device substitution. See “OTP address space” on page 49, “One Time Program Array commands” on page 118, and “OTP Read (OTPR 4Bh)” on page 118.
The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 1-KB OTP address range will yield indeterminate data.
The protocol of the OTP programming command is the same as Page Program. The OTP Program command can be issued multiple times to any given OTP address, but this address space can never be erased.
Automatic ECC is programmed on the first programming operation to each 16-byte region. Programming within a 16-byte region more than once disables the ECC. It is recommended to program each 16-byte portion of each 32-byte region once so that ECC remains enabled to provide the best data integrity.
The valid address range for OTP Program is depicted in Figure 43. OTP Program operations outside the valid OTP address range will be ignored and the WEL in SR1 will remain HIGH (set to 1). OTP Program operations while FREEZE = 1 will fail with P_ERR in SR1 set to ‘1’.
Infineon standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF) with a 128-bit random number using the Linear Congruential Random Number method. The seed value for the algorithm is a random number concatenated with the day and time of tester insertion.
The LSb of each Lock byte protects the lowest address region related to the byte, the MSb protects the highest address region related to the byte. The next higher address byte similarly protects the next higher eight regions. The LSb bit of the lowest address Lock Byte protects the higher address 16 bytes of the lowest address region. In other words, the LSb of location 0x10 protects all the Lock Bytes and RFU bytes in the lowest address region from further programming. See “OTP address space” on page 49.
The Write Enable (WREN) command must be written prior to any command that modifies non-volatile data. The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to ‘0’ (disables writes) during power-up, hardware reset, or after the device completes the following commands:
Reset
Page Program (PP)
Sector Erase (SE)
Bulk Erase (BE)
Write Disable (WRDI)
Write Registers (WRR)
Quad-input Page Programming (QPP)
OTP Byte Programming (OTPP)
The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register TBPROT bit can be used to protect an address range of the main flash array from program and erase operations. The size of the range is determined by the value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT bit of the configuration register.
Table 44 Upper array start of protection (TBPROT = 0)
Status Register content | Protected fraction of memory array | Protected memory (KB) | |||
BP2 | BP1 | BP0 | FL128S 128 Mb | FL256S 256 Mb | |
0 | 0 | 0 | None | 0 | 0 |
0 | 0 | 1 | Upper 64th | 256 | 512 |
0 | 1 | 0 | Upper 32nd | 512 | 1024 |
0 | 1 | 1 | Upper 16th | 1024 | 2048 |
1 | 0 | 0 | Upper 8th | 2048 | 4096 |
1 | 0 | 1 | Upper 4th | 4096 | 8192 |
1 | 1 | 0 | Upper half | 8192 | 16384 |
1 | 1 | 1 | All sectors | 16384 | 32768 |
Table 45 Lower array start of protection (TBPROT = 1)
Status Register content | Protected fraction of memory array | Protected memory (KB) | |||
BP2 | BP1 | BP0 | FL128S 128 Mb | FL256S 256 Mb | |
0 | 0 | 0 | None | 0 | 0 |
0 | 0 | 1 | Lower 64th | 256 | 512 |
0 | 1 | 0 | Lower 32nd | 512 | 1024 |
0 | 1 | 1 | Lower 16th | 1024 | 2048 |
1 | 0 | 0 | Lower 8th | 2048 | 4096 |
1 | 0 | 1 | Lower 4th | 4096 | 8192 |
1 | 1 | 0 | Lower half | 8192 | 16384 |
1 | 1 | 1 | All sectors | 16384 | 32768 |
When Block Protection is enabled (i.e., any BP2-0 are set to 1), Advanced Sector Protection (ASP) can still be used to protect sectors not protected by the Block Protection scheme. In the case that both ASP and Block Protection are used on the same sector the logical OR of ASP and Block Protection related to the sector is used. Recommen- dation: ASP and Block Protection should not be used concurrently. Use one or the other, but not both.
Bit 0 of the Configuration Register is the FREEZE bit. The FREEZE bit locks the BP2-0 bits in Status Register 1 and the TBPROT bit in the Configuration Register to their value at the time the FREEZE bit is set to ‘1’. Once the FREEZE bit has been written to a logic ‘1’ it cannot be cleared to a logic ‘0’ until a power-on-reset is executed. As long as the FREEZE bit is cleared to logic ‘0’ the status register BP bits and the TBPROT bit of the Configuration Register are writable. The FREEZE bit also protects the entire OTP memory space from programming when set to ‘1’. Any attempt to change the BP bits with the WRR command while FREEZE = 1 is ignored and no error status is set.
The Write Protect (WP#) input in combination with the Status Register Write Disable (SRWD) bit provide hardware input signal controlled protection. When WP# is LOW and SRWD is set to ‘1’, the Status and Configuration register is protected from alteration. This prevents disabling or changing the protection defined by the Block Protect bits.
Advanced Sector Protection (ASP) is the name used for a set of independent hardware and software methods used to disable or enable programming or erase operations, individually, in any or all sectors. An overview of these methods is shown in Figure 44.
PPB N-1
64-bit Password
(One Time Protect)
PPB N
DYB N-2
DYB N-1
DYB N
2) PPB are programmed individually 3) DYB are volatile bits but erased as a group
1) N = Highest Address Sector,
a sector is protected if its PPB =’0’ or its DYB = ‘0’
Dynamic Protection Bits (DYB)
Persistent Protection Bits (PPB)
PPB 0
Memory Array
7) Persistent Method only allows PPB Lock to be cleared to ‘0’ to prevent program or erase of PPB bits. Power off or hardware reset required to set PPB Lock to ‘1’
PPB Lock bit is volatile and defaults to ‘1’ (persistent mode), or ‘0’ (password mode) upon reset
PPB Lock = ‘0’ locks all PPBs to their current state
6) Password Method requires a password to set PPB Lock to ‘1’ to enable program or erase of PPB bits
PBB Lock Bit
PPB N-2
Sector N
Sector N -1
Sector N -2
PPB 2
PPB 1
DYB 2
DYB 1
DYB 0
Sector 2
Sector 1
Sector 0
‘0’ = PPBs locked
‘1’=PPBs unlocked
Block Protection and ASP protection settings for each sector are logically OR’d to define the protection for each sector, i.e. if either mechanism is protecting a sector the sector cannot be programmed or erased. See “Block protection” on page 64 for full details of the BP2-0 bits.
ASP Register One Time Programmable | ||
Password Method (ASPR[2]=0) | Persistent Method (ASPR[1]=0) | |
Figure 44 Advanced sector protection overview
Every main flash array sector has a non-volatile (PPB) and a volatile (DYB) protection bit associated with it. When either bit is 0, the sector is protected from program and erase operations.
The PPB bits are protected from program and erase when the PPB Lock bit is ‘0’. There are two methods for managing the state of the PPB Lock bit, Persistent Protection and Password Protection.
The Persistent Protection method sets the PPB Lock bit to ‘1’ during POR, or Hardware Reset so that the PPB bits are unprotected by a device reset. There is a command to clear the PPB Lock bit to ‘0’ to protect the PPB. There is no command in the Persistent Protection method to set the PPB Lock bit to 1, therefore the PPB Lock bit will remain at ‘0’ until the next power-off or hardware reset. The Persistent Protection method allows boot code the option of changing sector protection by programming or erasing the PPB, then protecting the PPB from further change for the remainder of normal system operation by clearing the PPB Lock bit to ‘0’. This is sometimes called Boot-code controlled sector protection.
The Password method clears the PPB Lock bit to ‘0’ during POR, or Hardware Reset to protect the PPB. A 64-bit password may be permanently programmed and hidden for the password method. A command can be used to provide a password for comparison with the hidden password. If the password matches, the PPB Lock bit is set to ‘1’ to unprotect the PPB. A command can be used to clear the PPB Lock bit to ‘0’. This method requires use of a password to control PPB protection.
The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP Register so as to permanently select the method used.
The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP) features (see
Table 34).
As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors unpro- tected, when power is applied. The device programmer or host system must then choose which sector protection method to use. Programming either of the, one-time programmable, Protection Mode Lock Bits, locks the part permanently in the selected mode:
ASPR[2:1] = 11 = No ASP mode selected, Persistent Protection Mode is the default.
ASPR[2:1] = 10 = Persistent Protection Mode permanently selected.
ASPR[2:1] = 01 = Password Protection Mode permanently selected.
ASPR[2:1] = 00 = Illegal condition, attempting to program both bits to ‘0’ results in a programming failure.
ASP register programming rules:
If the password mode is chosen, the password must be programmed prior to setting the Protection Mode Lock Bits.
Once the Protection Mode is selected, the Protection Mode Lock Bits are permanently protected from pro- gramming and no further changes to the ASP register is allowed.
The programming time of the ASP Register is the same as the typical page programming time. The system can determine the status of the ASP register programming operation by reading the WIP bit in the Status Register. See “Status Register 1 (SR1)” on page 51 for information on WIP.
After selecting a sector protection method, each sector can operate in each of the following states:
Dynamically Locked — A sector is protected and can be changed by a simple command.
Persistently Locked — A sector is protected and cannot be changed if its PPB Bit is ‘0’.
Unlocked — The sector is unprotected and can be changed by a simple command.
The Persistent Protection Bits (PPB) are located in a separate non-volatile flash array. One of the PPB bits is related to each sector. When a PPB is 0, its related sector is protected from program and erase operations. The PPB are programmed individually but must be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased at the same time. The PPB have the same program and erase endurance as the main flash memory array. Preprogramming and verification prior to erasure are handled by the device.
Programming a PPB bit requires the typical page programming time. Erasing all the PPBs requires typical sector erase time. During PPB bit programming and PPB bit erasing, status is available by reading the Status register. Reading of a PPB bit requires the initial access time of the device.
Notes:
Each PPB is individually programmed to ‘0’ and all are erased to ‘1’ in parallel.
If the PPB Lock bit is 0, the PPB Program or PPB Erase command does not execute and fails without programming or erasing the PPB.
The state of the PPB for a given sector can be verified by using the PPB Read command.
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYB only control the protection for sectors that have their PPB set to ‘1’. By issuing the DYB Write command, a DYB is cleared to ‘0’ or set to ‘1’, thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. The DYBs can be set or cleared as often as needed as they are volatile bits.
The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared to 0, it locks all PPBs and when set to 1, it allows the PPBs to be changed.
The PLBWR command is used to clear the PPB Lock bit to ‘0’. The PPB Lock Bit must be cleared to ‘0’ only after all the PPBs are configured to the desired settings.
In Persistent Protection mode, the PPB Lock is set to ‘1’ during POR or a hardware reset. When cleared to 0, no software command sequence can set the PPB Lock bit to 1, only another hardware reset or power-up can set the PPB Lock bit.
In the Password Protection mode, the PPB Lock bit is cleared to ‘0’ during POR or a hardware reset. The PPB Lock bit can only be set to ‘1’ by the Password Unlock command.
Each sector can be in one of the following protection states:
Unlocked — The sector is unprotected and protection can be changed by a simple command. The protection state defaults to unprotected after a power cycle, software reset, or hardware reset.
Dynamically Locked — A sector is protected and protection can be changed by a simple command. The protection state is not saved across a power cycle or reset.
Persistently Locked — A sector is protected and protection can only be changed if the PPB Lock Bit is set to ‘1’. The protection state is non-volatile and saved across a power cycle or reset. Changing the protection state requires programming and or erase of the PPB bits.
Table 46 Sector protection states
Protection bit values | Sector state | ||
PPB Lock | PPB | DYB | |
1 | 1 | 1 | Unprotected – PPB and DYB are changeable |
1 | 1 | 0 | Protected – PPB and DYB are changeable |
1 | 0 | 1 | Protected – PPB and DYB are changeable |
1 | 0 | 0 | Protected – PPB and DYB are changeable |
0 | 1 | 1 | Unprotected – PPB not changeable, DYB is changeable |
0 | 1 | 0 | Protected – PPB not changeable, DYB is changeable |
0 | 0 | 1 | Protected – PPB not changeable, DYB is changeable |
0 | 0 | 0 | Protected – PPB not changeable, DYB is changeable |
The Persistent Protection method sets the PPB Lock bit to ‘1’ during POR or Hardware Reset so that the PPB bits are unprotected by a device hardware reset. Software reset does not affect the PPB Lock bit. The PLBWR command can clear the PPB Lock bit to ‘0’ to protect the PPB. There is no command to set the PPB Lock bit therefore the PPB Lock bit will remain at ‘0’ until the next power-off or hardware reset.
Password Protection mode allows an even higher level of security than the Persistent Sector Protection Mode, by requiring a 64-bit password for unlocking the PPB Lock bit. In addition to this password requirement, after power up and hardware reset, the PPB Lock bit is cleared to ‘0’ to ensure protection at power-up. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock bit, allowing for sector PPB modifications.
Password Protection notes:
Once the Password is programmed and verified, the Password Mode (ASPR[2] = 0) must be set in order to prevent reading the password.
The Password Program Command is only capable of programming ‘0’s. Programming a ‘1’ after a cell is programmed as a ‘0’ results in the cell left as a ‘0’ with no programming error set.
The password is all ‘1’s when shipped from Infineon. It is located in its own memory space and is accessible through the use of the Password Program and Password Read commands.
All 64-bit password combinations are valid as a password.
The Password Mode, once programmed, prevents reading the 64-bit password and further password programming. All further program and read commands to the password region are disabled and these commands are ignored. There is no means to verify what the password is after the Password Mode Lock Bit is selected. Password verification is only allowed before selecting the Password Protection mode.
The Protection Mode Lock Bits are not erasable.
The exact password must be entered in order for the unlocking function to occur. If the password unlock command provided password does not match the hidden internal password, the unlock operation fails in the same manner as a programming operation on a protected sector. The P_ERR bit is set to one and the WIP Bit remains set. In this case it is a failure to change the state of the PPB Lock bit because it is still protected by the lack of a valid password.
The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly match a password. The Read Status Register 1 command may be used to read the WIP bit to determine when the device has completed the password unlock command or is ready to accept a new password command. When a valid password is provided the password unlock command does not insert the 100 µs delay before returning the WIP bit to ‘0’.
If the password is lost after selecting the Password Mode, there is no way to set the PPB Lock bit.
ECC status may only be read from sectors that are readable. In read protection mode the addresses are forced to the boot sector address. ECC status is shown in that sector while read protection mode is active.
All communication between the host system and S25FL128S and S25FL256S memory devices is in the form of units called commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All instruction, address, and data information is transferred serially between the host system and memory device.
All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.
Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to the host serially on SO signal.
Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.
Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3.
Commands are structured as follows:
Each command begins with an eight bit (byte) instruction.
The instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. The address may be either a 24-bit or 32-bit byte boundary address.
The Serial Peripheral Interface with Multiple IO provides the option for each transfer of address and data infor- mation to be done one, two, or four bits in parallel. This enables a trade off between the number of signal connections (IO bus width) and the speed of information transfer. If the host system can support a two or four bit wide IO bus the memory performance can be increased by using the instructions that provide parallel two bit (dual) or parallel four bit (Quad) transfers.
The width of all transfers following the instruction are determined by the instruction sent.
All single bits or parallel bit groups are transferred in most to least significant bit order.
Some instructions send instruction modifier (mode) bits following the address to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. The next command thus does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same command type is repeated in a sequence of commands.
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host.
Read latency may be ‘0’ to several SCK cycles (also referred to as dummy cycles).
All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted into the device with the most significant byte first. All data is transferred with the lowest address byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e., the byte address increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded operation. These are discussed in the individual command descriptions. While a program, erase, or write operation is in progress, it is recommended to check that the Write-In Progress (WIP) bit is ‘0’ before issuing most commands to the device, to ensure the new command can be accepted.
Depending on the command, the time for execution varies. A command to read status information from an executing command is available to determine when the command completes execution and whether the command was successful.
Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces of the host system and the memory device generally handle the details of signal relationships and timing. For this reason, signal relationships and timing are not covered in detail within this software interface focused section of the document. Instead, the focus is on the logical sequence of bits transferred in each command rather than the signal timing and relationships. Following are some general signal relationship descriptions to keep in mind. For additional information on the bit level format and signal timing relationships of commands, see “Command protocol” on page 21.
The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit wide transfers. The memory drives Serial Output (SO) for single bit read transfers. The host and memory alternately drive the IO0-IO3 signals during Dual and Quad transfers.
All commands begin with the host selecting the memory by driving CS# LOW before the first rising edge of SCK. CS# is kept LOW throughout a command and when CS# is returned high the command ends. Generally, CS# remains LOW for 8-bit transfer multiples to transfer byte granularity information. Some commands will not be accepted if CS# is returned HIGH not at an 8-bit boundary.
To accommodate addressing above 128 Mb, there are three options:
New instructions are provided with 4-byte address, used to access up to 32 Gb of memory.
Instruction name | Description | Code (Hex) |
4FAST_READ | Read Fast (4-byte address) | 0C |
4READ | Read (4-byte address) | 13 |
4DOR | Read Dual Out (4-byte address) | 3C |
4QOR | Read Quad Out (4-byte address) | 6C |
4DIOR | Dual I/O Read (4-byte address) | BC |
4QIOR | Quad I/O Read (4-byte address) | EC |
4DDRFR | Read DDR Fast (4-byte address) | 0E |
4DDRDIOR | DDR Dual I/O Read (4-byte address) | BE |
4DDRQIOR | DDR Quad I/O Read (4-byte address) | EE |
4PP | Page Program (4-byte address) | 12 |
4QPP | Quad Page Program (4-byte address) | 34 |
4P4E | Parameter 4-KB Erase (4-byte address) | 21 |
4SE | Erase 64/256 KB (4-byte address) | DC |
For backward compatibility to the 3-byte address instructions, the standard instructions can be used in conjunction with the EXTADD Bit in the Bank Address Register (BAR[7]). By default BAR[7] is cleared to ‘0’ (following power up and hardware reset), to enable 3-byte (24-bit) addressing. When set to 1, the legacy commands are changed to require 4 bytes (32 bits) for the address field. The following instructions can be used in conjunction with EXTADD bit to switch from 3 bytes to 4 bytes of address field.
Instruction name | Description | Code (Hex) |
READ | Read (3-byte address) | 03 |
FAST_READ | Read Fast (3-byte address) | 0B |
DOR | Read Dual Out (3-byte address) | 3B |
QOR | Read Quad Out (3-byte address) | 6B |
DIOR | Dual I/O Read (3-byte address) | BB |
QIOR | Quad I/O Read (3-byte address) | EB |
Instruction name | Description | Code (Hex) |
DDRFR | Read DDR Fast (3-byte address) | 0D |
DDRDIOR | DDR Dual I/O Read (3-byte address) | BD |
DDRQIOR | DDR Quad I/O Read (3-byte address) | ED |
PP | Page Program (3-byte address) | 02 |
QPP | Quad Page Program (3-byte address) | 32 |
P4E | Parameter 4-KB Erase (3-byte address) | 20 |
SE | Erase 64 / 256 KB (3-byte address) | D8 |
For backward compatibility to the 3-byte addressing, the standard instructions can be used in conjunction with the Bank Address Register:
a.The Bank Address Register is used to switch between 128-Mb (16-MB) banks of memory, The standard 3-byte address selects an address within the bank selected by the Bank Address Register.
The host system writes the Bank Address Register to access beyond the first 128 Mb of memory.
This applies to read, erase, and program commands.
a. The Bank Register provides the high order (4th) byte of address, which is used to address the available memory at addresses greater than 16 MB.
a. Bank Register bits are volatile.
i. On power up, the default is Bank0 (the lowest address 16 MB).
a. For Read, the device will continuously transfer out data until the end of the array.
There is no bank to bank delay.
The Bank Address Register is not updated.
The Bank Address Register value is used only for the initial address of an access.
Table 47 Bank address map
Bank Address Register bits | Bank | Memory array address range (Hex) | ||
Bit 1 | Bit 0 | |||
0 | 0 | 0 | 00000000 | 00FFFFFF |
0 | 1 | 1 | 01000000 | 01FFFFFF |
Table 48 S25FL128S and S25FL256S command set (Sorted by function)
Function | Command name | Command description | Instruction value (Hex) | Maximum frequency (MHz) |
Read Device Identification | READ_ID (REMS) | Read Electronic Manufacturer Signature | 90 | 133 |
RDID | Read ID (JEDEC Manufacturer ID and JEDEC CFI) | 9F | 133 | |
RES | Read Electronic Signature | AB | 50 | |
Register Access | RDSR1 | Read Status Register-1 | 05 | 133 |
RDSR2 | Read Status Register-2 | 07 | 133 | |
RDCR | Read Configuration Register-1 | 35 | 133 | |
WRR | Write Register (Status-1, Configuration-1) | 01 | 133 | |
WRDI | Write Disable | 04 | 133 | |
WREN | Write Enable | 06 | 133 | |
CLSR | Clear Status Register-1 - Erase/Program Fail Reset | 30 | 133 | |
ECCRD | ECC Read (4-byte address) | 18 | 133 | |
ABRD | AutoBoot Register Read | 14 | 133 (QUAD=0) 104 (QUAD=1) | |
ABWR | AutoBoot Register Write | 15 | 133 | |
BRRD | Bank Register Read | 16 | 133 | |
BRWR | Bank Register Write | 17 | 133 | |
BRAC | Bank Register Access (Legacy command formerly used for Deep Power Down) | B9 | 133 | |
DLPRD | Data Learning Pattern Read | 41 | 133 | |
PNVDLR | Program NV Data Learning Register | 43 | 133 | |
WVDLR | Write Volatile Data Learning Register | 4A | 133 | |
Read Flash Array | READ | Read (3- or 4-byte address) | 03 | 50 |
Read Flash Array | 4READ | Read (4-byte address) | 13 | 50 |
FAST_READ | Fast Read (3- or 4-byte address) | 0B | 133 | |
4FAST_READ | Fast Read (4-byte address) | 0C | 133 | |
DDRFR | DDR Fast Read (3- or 4-byte address) | 0D | 80 | |
4DDRFR | DDR Fast Read (4-byte address) | 0E | 80 | |
DOR | Read Dual Out (3- or 4-byte address) | 3B | 104 | |
4DOR | Read Dual Out (4-byte address) | 3C | 104 | |
QOR | Read Quad Out (3- or 4-byte address) | 6B | 104 | |
4QOR | Read Quad Out (4-byte address) | 6C | 104 | |
DIOR | Dual I/O Read (3- or 4-byte address) | BB | 104 | |
4DIOR | Dual I/O Read (4-byte address) | BC | 104 | |
DDRDIOR | DDR Dual I/O Read (3- or 4-byte address) | BD | 80 |
Table 48 S25FL128S and S25FL256S command set (Sorted by function) (continued)
Function | Command name | Command description | Instruction value (Hex) | Maximum frequency (MHz) |
Read Flash Array | 4DDRDIOR | DDR Dual I/O Read (4-byte address) | BE | 80 |
QIOR | Quad I/O Read (3- or 4-byte address) | EB | 104 | |
4QIOR | Quad I/O Read (4-byte address) | EC | 104 | |
DDRQIOR | DDR Quad I/O Read (3- or 4-byte address) | ED | 80 | |
4DDRQIOR | DDR Quad I/O Read (4-byte address) | EE | 80 | |
Program Flash Array | PP | Page Program (3- or 4-byte address) | 02 | 133 |
4PP | Page Program (4-byte address) | 12 | 133 | |
QPP | Quad Page Program (3- or 4-byte address) | 32 | 80 | |
QPP | Quad Page Program - Alternate instruction (3- or 4-byte address) | 38 | 80 | |
4QPP | Quad Page Program (4-byte address) | 34 | 80 | |
PGSP | Program Suspend | 85 | 133 | |
PGRS | Program Resume | 8A | 133 | |
Erase Flash Array | P4E | Parameter 4-KB, sector Erase (3- or 4-byte address) | 20 | 133 |
4P4E | Parameter 4-KB, sector Erase (4-byte address) | 21 | 133 | |
BE | Bulk Erase | 60 | 133 | |
BE | Bulk Erase (alternate command) | C7 | 133 | |
SE | Erase 64 KB or 256 KB (3- or 4-byte address) | D8 | 133 | |
4SE | Erase 64 KB or 256 KB (4-byte address) | DC | 133 | |
ERSP | Erase Suspend | 75 | 133 | |
ERRS | Erase Resume | 7A | 133 | |
One Time Program Array | OTPP | OTP Program | 42 | 133 |
OTPR | OTP Read | 4B | 133 | |
Advanced Sector Protection | DYBRD | DYB Read | E0 | 133 |
DYBWR | DYB Write | E1 | 133 | |
PPBRD | PPB Read | E2 | 133 | |
PPBP | PPB Program | E3 | 133 | |
PPBE | PPB Erase | E4 | 133 | |
ASPRD | ASP Read | 2B | 133 | |
ASPP | ASP Program | 2F | 133 | |
Advanced Sector Protection | PLBRD | PPB Lock Bit Read | A7 | 133 |
PLBWR | PPB Lock Bit Write | A6 | 133 | |
PASSRD | Password Read | E7 | 133 | |
PASSP | Password Program | E8 | 133 | |
PASSU | Password Unlock | E9 | 133 |
Table 48 S25FL128S and S25FL256S command set (Sorted by function) (continued)
Function | Command name | Command description | Instruction value (Hex) | Maximum frequency (MHz) |
Reset | RESET | Software Reset | F0 | 133 |
MBR | Mode Bit Reset | FF | 133 | |
Reserved for Future Use | MPM | Reserved for Multi-I/O-High Perf Mode (MPM) | A3 | 133 |
RFU | Reserved-18 | Reserved | 18 | – |
RFU | Reserved-E5 | Reserved | E5 | – |
RFU | Reserved-E6 | Reserved | E6 | – |
There are multiple commands to read information about the device manufacturer, device type, and device features. SPI memories from different vendors have used different commands and formats for reading infor- mation about the memories. The S25FL128S and S25FL256S devices support the three most common device information commands.
There are multiple registers for reporting embedded operation status or controlling device configuration options. There are commands for reading or writing these registers. Registers contain both volatile and non-volatile bits. Non-volatile bits in registers are automatically erased and programmed as a single (write) operation.
The host system can determine when a write, program, erase, suspend or other embedded operation is complete by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register-1 command provides the state of the WIP bit. The program error (P_ERR) and erase error (E_ERR) bits in the status register indicate whether the most recent program or erase command has not completed successfully. When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains busy. Under this condition, only the CLSR, WRDI, RDSR1, RDSR2, and software RESET commands are valid commands. A Clear Status Register (CLSR) followed by a Write Disable (WRDI) command must be sent to return the device to standby state. CLSR clears the WIP, P_ERR, and E_ERR bits. WRDI clears the WEL bit. Alternatively, Hardware Reset, or Software Reset (RESET) may be used to return the device to standby state.
There are commands to read, write, and protect registers that control interface path width, interface timing, interface address length, and some aspects of data protection.
Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from incre- mentally higher byte addresses until the host ends the data transfer by driving CS# input HIGH. If the byte address reaches the maximum address of the memory array, the read will continue at address ‘0’ of the array.
There are several different read commands to specify different access latency and data path widths. Double Data Rate (DDR) commands also define the address and data bit relationship to both SCK edges:
The Read command provides a single address bit per SCK rising edge on the SI signal with read data returning a single bit per SCK falling edge on the SO signal. This command has ‘0’ latency between the address and the returning data but is limited to a maximum SCK rate of 50 MHz.
Other read commands have a latency period between the address and returning data but can operate at higher SCK frequencies. The latency depends on the configuration register latency code.
The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data returning a single bit per SCK falling edge on the SO signal and may operate up to 133 MHz.
Dual or Quad Output read commands provide address a single bit per SCK rising edge on the SI / IO0 signal with read data returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.
Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.
Fast (Single), Dual, or Quad Double Data Rate read commands provide address one bit, two bits or four bits per every SCK edge with read data returning one bit, two bits, or four bits of data per every SCK edge on the IO0-IO3 signals. Double Data Rate (DDR) operation is only supported for core and I/O voltages of 3 to 3.6V.
Programming data requires two commands: Write Enable (WREN), and Page Program (PP or QPP). The Page Program command accepts from 1-byte up to 256 or 512 consecutive bytes of data (page) to be programmed in one operation. Programming means that bits can either be left at ‘1’, or programmed from ‘1’ to ‘0’. Changing bits from ‘0’ to ‘1’ requires an erase operation.
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to ‘1’. A bit needs to be first erased to ‘1’ before programming can change it to a ‘0’. While bits can be individually programmed from a ‘1’ to ‘0’, erasing bits from ‘0’ to ‘1’ must be done on a sector-wide (SE) or array-wide (BE) level.
There are commands to read and program a separate One Time Programmable (OTP) array for permanent data such as a serial number. There are commands to control a contiguous group (block) of flash memory array sectors that are protected from program and erase operations. There are commands to control which individual flash memory array sectors are protected from program and erase operations.
There is a command to reset to the default conditions present after power on to the device. There is a command to reset (exit from) the Enhanced Performance Read Modes.
Some instructions are reserved for future use. In this generation of the S25FL128S and S25FL256S some of these command instructions may be unused and not affect device operation, some may have undefined results.
Some commands are reserved to ensure that a legacy or alternate source device command is allowed without affect. This allows legacy software to issue some commands that are not relevant for the current generation S25FL128S and S25FL256S devices with the assurance these commands do not cause some unexpected action.
Some commands are reserved for use in special versions of the FL-S not addressed by this document or for a future generation. This allows new host memory controller designs to plan the flexibility to issue these command instructions. The command format is defined if known at the time this document revision is published.
The READ_ID command identifies the Device Manufacturer ID and the Device ID. The command is also referred to as Read Electronic Manufacturer and device Signature (REMS). READ-ID (REMS) is only supported for backward compatibility and should not be used for new software designs. New software designs should instead make use of the RDID command.
The command is initiated by shifting on SI the instruction code “90h” followed by a 24-bit address of 00000h. Following this, the Manufacturer ID and the Device ID are shifted out on SO starting at the falling edge of SCK after address. The Manufacturer ID and the Device ID are always shifted out with the MSb first. If the 24-bit address is set to 000001h, then the Device ID is read out first followed by the Manufacturer ID. The Manufacturer ID and Device ID output data toggles between address 000000H and 000001H until terminated by a low to high transition on CS# input. The maximum clock frequency for the READ_ID command is 133 MHz.
90h
SI
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
CS#
SO
23 22 21 3 2 1 0
MSb
7
MSb
SI
ADD (1)
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
Device ID
6 5 4 3 2 1 0
High Impedance
Manufacture ID
7 6 5 4 3 2 1 0
MSb
Figure 45 READ_ID command sequence
Table 49 Read_ID values
Device | Manufacturer ID (Hex) | Device ID (Hex) |
S25FL128S | 01 | 17 |
S25FL256S | 01 | 18 |
The Read Identification (RDID) command provides read access to manufacturer identification, device identifi- cation, and Common Flash Interface (CFI) information. The manufacturer identification is assigned by JEDEC. The CFI structure is defined by JEDEC standard. The device identification and CFI values are assigned by Infineon.
The JEDEC Common Flash Interface (CFI) specification defines a device information structure, which allows a vendor-specified software flash management program (driver) to be used for entire families of flash devices. Software support can then be device-independent, JEDEC manufacturer ID independent, forward and backward-compatible for the specified flash device families. System vendors can standardize their flash drivers for long-term software compatibility by using the CFI values to configure a family driver from the CFI information of the device in use.
Any RDID command issued while a program, erase, or write cycle is in progress is ignored and has no effect on execution of the program, erase, or write cycle that is in progress.
The RDID instruction is shifted on SI. After the last bit of the RDID instruction is shifted into the device, a byte of manufacturer identification, two bytes of device identification, extended device identification, and CFI infor- mation will be shifted sequentially out on SO. As a whole this information is referred to as ID-CFI. See “ID-CFI address space” on page 49 for the detail description of the ID-CFI contents.
Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data. The RDID command sequence is terminated by driving CS# to the logic HIGH state anytime during data output.
The maximum clock frequency for the RDID command is 133 MHz.
Extended Device Information
Manufacturer / Device Identification
SI
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 652 653 654 655
C S#
High Impedance
SO
0 1 2 20 21 22 23 24 25 26
644 645 646 1 647
Figure 46 Read Identification (RDID) command sequence
The RES command is used to read a single byte Electronic Signature from SO. RES is only supported for backward compatibility and should not be used for new software designs. New software designs should instead make use of the RDID command.
The RES instruction is shifted in followed by three dummy bytes onto SI. After the last bit of the three dummy bytes are shifted into the device, a byte of Electronic Signature will be shifted out of SO. Each bit is shifted out by the falling edge of SCK. The maximum clock frequency for the RES command is 50 MHz.
The Electronic Signature can be read repeatedly by applying multiples of eight clock cycles.
The RES command sequence is terminated by driving CS# to the logic HIGH state anytime during data output.
0
2 1
23 22 21 3
MSb
SI
3 Dummy Bytes
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CS#
SO
High Impedance
Electonic ID
7 6 5 4 3 2 1 0
MSb
Figure 47 Read Electronic Signature (RES) command sequence
Table 50 RES values
Device | Device ID (Hex) |
S25FL128S | 17 |
S25FL256S | 18 |
The Read Status Register-1 (RDSR1) command allows the Status Register-1 contents to be read from SO. The Status Register-1 contents may be read at any time, even while a program, erase, or write operation is in progress. It is possible to read the Status Register-1 continuously by providing multiples of eight clock cycles. The status is updated for each eight cycle read. The maximum clock frequency for the RDSR1 (05h) command is 133 MHz.
MSb
CS#
MSb
Status Register-1 Out
6 5 4 3 2 1 0 7
7
MSb
Status Register-1 Out
7 6 5 4 3 2 1 0
SO
High Impedance
SI
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Figure 48 Read Status Register-1 (RDSR1) command sequence
The Read Status Register (RDSR2) command allows the Status Register-2 contents to be read from SO. The Status Register-2 contents may be read at any time, even while a program, erase, or write operation is in progress. It is possible to read the Status Register-2 continuously by providing multiples of eight clock cycles. The status is updated for each eight cycle read. The maximum clock frequency for the RDSR2 command is 133 MHz.
7
MSb
SO
7 6 5 4 3 2 1 0
High Impedance
SI
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS#
Status Register-2 Out
6 5 4 3 2 1 0
7
MSb
Status Register-2 Out
6 5 4 3 2 1 0 7
MSb
Figure 49 Read Status Register-2 (RDSR2) command
CS# SCK
SI SO
Phase
The Read Configuration Register (RDCR) command allows the Configuration Register contents to be read from SO. It is possible to read the Configuration Register continuously by providing multiples of eight clock cycles. The Configuration Register contents may be read at any time, even while a program, erase, or write operation is in progress.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Instruction | Register Read | Repeat Register Read |
Figure 50 Read Configuration Register (RDCR) command sequence
The Read the Bank Register (BRRD) command allows the Bank address Register contents to be read from SO. The instruction is first shifted in from SI. Then the 8-bit Bank Register is shifted out on SO. It is possible to read the Bank Register continuously by providing multiples of eight clock cycles. The maximum operating clock frequency for the BRRD command is 133 MHz.
SCK
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MSb MSb MSb
Instruction
SI
7 6 5 4 3 2 1 0
MSB
Bank Register Out
Bank Register Out
High Impedance
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Figure 51 Read Bank Register (BRRD) command
The Bank Register Write (BRWR) command is used to write address bits above A23, into the Bank Address Register (BAR). The command is also used to write the Extended address control bit (EXTADD) that is also in BAR[7]. BAR provides the high order addresses needed by devices having more than 128 Mb (16 MB), when using 3-byte address commands without extended addressing enabled (BAR[7] EXTADD = 0). Because this command is part of the addressing method and is not changing data in the flash memory, this command does not require the WREN command to precede it.
The BRWR instruction is entered, followed by the data byte on SI. The Bank Register is one data byte in length.
The BRWR command has no effect on the P_ERR, E_ERR or WIP bits of the Status and Configuration Registers. Any bank address bit reserved for the future should always be written as a ‘0’.
SI
Bank Register In
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CS#
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSb MSb
SO
High Impedance
Figure 52 Bank Register Write (BRWR) command
The Bank Register Read and Write commands provide full access to the Bank Address Register (BAR) but they are both commands that are not present in legacy SPI memory devices. Host system SPI memory controller inter- faces may not be able to easily support such new commands. The Bank Register Access (BRAC) command uses the same command code and format as the Deep Power Down (DPD) command that is available in legacy SPI memories. The FL-S family does not support a DPD feature but assigns this legacy command code to the BRAC command to enable write access to the Bank Address Register for legacy systems that are able to send the legacy DPD (B9h) command.
When the BRAC command is sent, the FL-S family device will then interpret an immediately following Write Register (WRR) command as a write to the lower address bits of the BAR. A WREN command is not used between the BRAC and WRR commands. Only the lower two bits of the first data byte following the WRR command code are used to load BAR[1:0]. The upper bits of that byte and the content of the optional WRR command second data byte are ignored. Following the WRR command, the access to BAR is closed and the device interface returns to the standby state. The combined BRAC followed by WRR command sequence has no affect on the value of the ExtAdd bit (BAR[7]).
Commands other than WRR may immediately follow BRAC and execute normally. However, any command other than WRR, or any other sequence in which CS# goes LOW and returns HIGH, following a BRAC command, will close the access to BAR and return to the normal interpretation of a WRR command as a write to Status Register-1 and the Configuration Register.
The BRAC + WRR sequence is allowed only when the device is in standby, program suspend, or erase suspend states. This command sequence is illegal when the device is performing an embedded algorithm or when the program (P_ERR) or erase (E_ERR) status bits are set to ‘1’.
CS#
SO
7 6 5 4 3 2 1 0
MSb
High Impedance
SI
Instruction
SCK
0 1 2 3 4 5 6 7
Figure 53 BRAC (B9h) command sequence
The Write Registers (WRR) command allows new values to be written to both the Status Register-1 and Configu- ration Register. Before the Write Registers (WRR) command can be accepted by the device, a Write Enable (WREN) command must be received. After the Write Enable (WREN) command has been decoded successfully, the device will set the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The Write Registers (WRR) command is entered by shifting the instruction and the data bytes on SI. The Status Register is one data byte in length.
The Write Registers (WRR) command will set the P_ERR or E_ERR bits if there is a failure in the WRR operation. Any Status or Configuration Register bit reserved for the future must be written as a ‘0’.
CS# must be driven to the logic HIGH state after the eighth or sixteenth bit of data has been latched. If not, the Write Registers (WRR) command is not executed. If CS# is driven HIGH after the eighth cycle then only the Status Register-1 is written; otherwise, after the sixteenth cycle both the Status and Configuration Registers are written. When the configuration register QUAD bit CR[1] is ‘1’, only the WRR command format with 16 data bits may be used.
As soon as CS# is driven to the logic HIGH state, the self-timed Write Registers (WRR) operation is initiated. While the Write Registers (WRR) operation is in progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a ‘1’ during the self-timed Write Registers (WRR) operation, and is a ‘0’ when it is completed. When the Write Registers (WRR) operation is completed, the Write Enable Latch (WEL) is set to a ‘0’. The WRR command must be executed under continuous power. The maximum clock frequency for the WRR command is 133 MHz.
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CS#
High Impedance
SO
4 3 2 1 0
6 5
7
MSb
Status Register In
SI
Figure 54 Write Registers (WRR) command sequence – 8 data bits
CS#
6 5 4 3 2
7
MSb
SI
Configuration Register In
Status Register In
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1 0
High Impedance
7
MSb
6 5 4 3 2 1 0
SO
Figure 55 Write Registers (WRR) command sequence – 16 data bits
The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1, and BP0) bits to define the size of the area that is to be treated as read-only. The Write Registers (WRR) command also allows the user to set the Status Register Write Disable (SRWD) bit to a ‘1’ or a ‘0’. The Status Register Write Disable (SRWD) bit and Write Protect (WP#) signal allow the BP bits to be hardware protected.
When the Status Register Write Disable (SRWD) bit of the Status Register is a ‘0’ (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) command, regardless of the whether Write Protect (WP#) signal is driven to the logic HIGH or logic LOW state.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to a ‘1’, two cases need to be considered, depending on the state of Write Protect (WP#):
If Write Protect (WP#) signal is driven to the logic HIGH state, it is possible to write to the Status and Configuration Registers provided that the Write Enable Latch (WEL) bit has previously been set to a ‘1’ by initiating a Write Enable (WREN) command.
If Write Protect (WP#) signal is driven to the logic LOW state, it is not possible to write to the Status and Config- uration Registers even if the Write Enable Latch (WEL) bit has previously been set to a ‘1’ by a Write Enable (WREN) command. Attempts to write to the Status and Configuration Registers are rejected, and are not accepted for execution. As a consequence, all the data bytes in the memory area that are protected by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected by WP#.
The WP# hardware protection can be provided:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic LOW state;
or by driving Write Protect (WP#) signal to the logic LOW state after setting the Status Register Write Disable (SRWD) bit to a ‘1’.
The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic HIGH state. If WP# is permanently tied HIGH, hardware protection of the BP bits can never be activated.
Table 51 Block Protection modes
WP# | SRWD bit | Mode | Write Protection of Registers | Memory content | |
Protected area | Unprotected area | ||||
1 | 1 | Software Protected | Status and Configuration Registers are Writable (if WREN command has set the WEL bit). The values in the SRWD, BP2, BP1, and BP0 bits and those in the Configuration Register can be changed. | Protected against Page Program, Quad Input Program, Sector Erase, and Bulk Erase | Ready to accept Page Program, Quad Input Program and Sector Erase commands |
1 | 0 | ||||
0 | 0 | ||||
0 | 1 | Hardware Protected | Status and Configuration Registers are Hardware Write Protected. The values in the SRWD, BP2, BP1, and BP0 bits and those in the Configuration Register cannot be changed. | Protected against Page Program, Sector Erase, and Bulk Erase | Ready to accept Page Program or Erase commands |
Notes
The Status Register originally shows 00h when the device is first shipped from Infineon to the customer.
Hardware protection is disabled when Quad Mode is enabled (QUAD bit = 1 in Configuration Register). WP# becomes IO2; therefore, it cannot be utilized.
The WRR command has an alternate function of loading the Bank Address Register if the command immediately follows a BRAC command. See “Bank Register Access (BRAC B9h)” on page 80.
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1[1]) to a ‘1’. The Write Enable Latch (WEL) bit must be set to a ‘1’ by issuing the Write Enable (WREN) command to enable write, program and erase commands.
CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being driven to the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI, the write enable operation will not be executed.
CS#
0 1 2 3 4 5 6 7
SCK
Instruction
SI
Figure 56 Write Enable (WREN) command sequence
The Write Disable (WRDI) command sets the Write Enable Latch (WEL) bit of the Status Register-1 (SR1[1]) to a ‘0’.
The Write Enable Latch (WEL) bit may be set to a ‘0’ by issuing the Write Disable (WRDI) command to disable Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR), OTP Program (OTPP), and other commands, that require WEL be set to ‘1’ for execution. The WRDI command can be used by the user to protect memory areas against inadvertent writes that can possibly corrupt the contents of the memory. The WRDI command is ignored during an embedded operation while WIP bit =1.
CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being driven to the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI, the write disable operation will not be executed.
CS#
0 1 2 3 4 5 6 7
SCK
Instruction
SI
Figure 57 Write Disable (WRDI) command sequence
The Clear Status Register command resets bit SR1[5] (Erase Fail Flag) and bit SR1[6] (Program Fail Flag). It is not necessary to set the WEL bit before the Clear SR command is executed. The Clear SR command will be accepted even when the device remains busy with WIP set to 1, as the device does remain busy when either error bit is set. The WEL bit will be unchanged after this command is executed.
SI
Instruction
SCK
7
6
4 5
3
1 2
0
CS#
Figure 58 Clear Status Register (CLSR) command sequence
To read the ECC Status Register, the command is followed by the ECC unit (32 bit) address, the four least signif- icant bits (LSb) of address must be set to ‘0’. This is followed by eight dummy cycles. Then the 8-bit contents of the ECC Register, for the ECC unit selected, are shifted out on SO 16 times, once for each byte in the ECC Unit. If CS# remains LOW, the next ECC unit status is sent through SO 16 times, once for each byte in the ECC Unit, this continues until CS# goes HIGH. The maximum operating clock frequency for the ECC READ command is 133 MHz. See “Automatic ECC” on page 106 for details on ECC unit.
1 0 7
MSb
DATA OUT 2
DATA OUT 1
6 5 4 3 2
SO High Impedance 7
MSb
7 6 5 4 3 2 1 0 31 30 29 3 2 1 0 7 6 5 4 3 2 1 0
SI
Dummy Byte
32-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CS#
Figure 59 ECC Status Register Read command sequence
SPI devices normally require 32 or more cycles of command and address shifting to initiate a read command. And, in order to read boot code from an SPI device, the host memory controller or processor must supply the read command from a hardwired state machine or from some host processor internal ROM code.
Parallel NOR devices need only an initial address, supplied in parallel in a single cycle, and initial access time to start reading boot code.
The AutoBoot feature allows the host memory controller to take boot code from an S25FL128S and S25FL256S device immediately after the end of reset, without having to send a read command. This saves 32 or more cycles and simplifies the logic needed to initiate the reading of boot code.
As part of the power up reset, hardware reset, or command reset process the AutoBoot feature automatically starts a read access from a pre-specified address. At the time the reset process is completed, the device is ready to deliver code from the starting address. The host memory controller only needs to drive CS# signal from HIGH to LOW and begin toggling the SCK signal. The S25FL128S and S25FL256S device will delay code output for a pre-specified number of clock cycles before code streams out.
The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is needed by the host.
The host cannot send commands during this time. If ABSD = 0, the maximum SCK frequency is 50 MHz.
If ABSD > 0, the maximum SCK frequency is 133 MHz if the QUAD bit CR1[1] is ‘0’ or 104 MHz if the QUAD bit is
set to ‘1’.
The starting address of the boot code is selected by the value programmed into the AutoBoot Start Address (ABSA) field of the AutoBoot Register which specifies a 512-byte boundary aligned location; the default address is 00000000h.
Data will continuously shift out until CS# returns HIGH.
At any point after the first data byte is transferred, when CS# returns HIGH, the SPI device will reset to standard SPI mode; able to accept normal command operations.
A minimum of one byte must be transferred.
AutoBoot mode will not initiate again until another power cycle or a reset occurs.
An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.
The AutoBoot register bits are non-volatile and provide:
The starting address (512-byte boundary), set by the AutoBoot Start Address (ABSA). The size of the ABSA field is 23-bits for devices up to 32-Gb.
The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 8-bit count value.
The AutoBoot Enable.
If the configuration register QUAD bit CR1[1] is set to 1, the boot code will be provided 4 bits per cycle in the same manner as a Read Quad Out command. If the QUAD bit is ‘0’ the code is delivered serially in the same manner as a Read command.
DATA OUT 1 DATA OUT 2
7 6 5 4 3 2 1 0 7
MSb MSb
High Impedance
SO
Don’t Care or High Impedance
SI
Wait State tWS
SCK
0 - - - - - - n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9
CS#
Figure 60 AutoBoot sequence (CR1[1] = 0)
CS#
0 - - - - - - n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9
SCK
Wait State tWS
IO0
High Impedance
4 0 4 0 4 0 4 0 4
DATA OUT 1
High Impedance
IO1
5 1 5 1 5 1 5 1 5
IO2
High Impedance
6 2 6 2 6 2 6 2 6
IO3
High Impedance
7
MSb
3 7
3 7 3 7 3 7
Figure 61 AutoBoot sequence (CR1[1] = 1)
The AutoBoot Register Read command is shifted into SI. Then the 32-bit AutoBoot Register is shifted out on SO, least significant byte first, most significant bit of each byte first. It is possible to read the AutoBoot Register contin- uously by providing multiples of 32 clock cycles. If the QUAD bit CR1[1] is cleared to 0, the maximum operating clock frequency for ABRD command is 133 MHz. If the QUAD bit CR1[1] is set to 1, the maximum operating clock frequency for ABRD command is 104 MHz.
7 6 5 4
SO
High Impedance
CS#
1 0
6 5 4 3 2
7
MSb
SI
Instruction
SCK
37 38 39 40
0 1 2 3 4 5 6 7 8 9 10 11
26 25 24 7
MSb MSb
AutoBoot Register
Figure 62 AutoBoot Register Read (ABRD) command
Before the ABWR command can be accepted, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The ABWR command is entered by shifting the instruction and the data bytes on SI, least significant byte first, most significant bit of each byte first. The ABWR data is 32-bits in length.
The ABWR command has status reported in Status Register-1 as both an erase and a programming operation. An E_ERR or a P_ERR may be set depending on whether the erase or programming phase of updating the register fails.
CS# must be driven to the logic HIGH state after the 32nd bit of data has been latched. If not, the ABWR command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed ABWR operation is initiated. While the ABWR operation is in progress, Status Register-1 may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a ‘1’ during the self-timed ABWR operation, and is a ‘0’. when it is completed. When the ABWR cycle is completed, the Write Enable Latch (WEL) is set to a ‘0’. The maximum clock frequency for the ABWR command is 133 MHz.
CS#
7 6 5 4 3 2 1 0
MSb
SI
AutoBoot Register
Instruction
SCK
36 37 38 39
0 1 2 3 4 5 6 7 8 9 10
6 5
27 26 25 24
SO
High Impedance
7
MSb
Figure 63 AutoBoot Register Write (ABWR) command
Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded success- fully, the device will set the Write Enable Latch (WEL) to enable the PNVDLR operation.
The PNVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic HIGH state after the eighth (8th) bit of data has been latched. If not, the PNVDLR command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PNVDLR operation is initiated. While the PNVDLR operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a ‘1’ during the self-timed PNVDLR cycle, and is a ‘0’. when it is completed. The PNVDLR operation can report a program error in the P_ERR bit of the status register. When the PNVDLR operation is completed, the Write Enable Latch (WEL) is set to a ‘0’ The maximum clock frequency for the PNVDLR command is 133 MHz.
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSb MSb
SI
Data Learning Pattern
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CS#
High Impedance
Figure 64 Program NVDLR (PNVDLR) command sequence
Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the Write Enable Latch (WEL) to enable WVDLR operation.
The WVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic HIGH state after the eighth (8th) bit of data has been latched. If not, the WVDLR command is not executed. As soon as CS# is driven to the logic HIGH state, the WVDLR operation is initiated with no delays. The maximum clock frequency for the PNVDLR command is 133 MHz.
SO
MSb
MSb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SI
Data Learning Pattern
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CS#
High Impedance
Figure 65 Write VDLR (WVDLR) command sequence
The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP continuously by providing multiples of eight clock cycles. The maximum operating clock frequency for the DLPRD command is 133 MHz.
7
MSb
4 3 2 1 0
6 5
7
MSb
CS#
SO
7 6 5 4 3 2 1 0
MSb
SI
Data Learning Pattern
Data Learning Pattern
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
6 5 4 3 2 1 0
High Impedance
Figure 66 DLP Read (DLPRD) command sequence
Read commands for the main flash array provide many options for prior generation SPI compatibility or enhanced performance SPI:
Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate commands (SDR).
Some SDR commands transfer address one bit per rising edge of SCK and return data 1-, 2-, or 4-bits of data per rising edge of SCK. These are called Read or Fast Read for 1-bit data; Dual Output Read for 2-bit data, and Quad Output for 4-bit data.
Some SDR commands transfer both address and data 2- or 4-bits per rising edge of SCK. These are called Dual I/O for 2-bit and Quad I/O for 4-bit.
Some commands transfer address and data on both the rising edge and falling edge of SCK. These are called Double Data Rate (DDR) commands.
There are DDR commands for 1-, 2-, or 4-bits of address or data per SCK edge. These are called Fast DDR for 1-bit, Dual I/O DDR for 2-bit, and Quad I/O DDR for 4-bit per edge transfer.
All of these commands begin with an instruction code that is transferred one bit per SCK rising edge. The instruction is followed by either a 3- or 4-byte address transferred at SDR or DDR. Commands transferring address or data 2- or 4-bits per clock edge are called Multiple I/O (MIO) commands. For FL-S devices at 256 Mb or higher density, the traditional SPI 3-byte addresses are unable to directly address all locations in the memory array.
These device have a bank address register that is used with 3-byte address commands to supply the high order address bits beyond the address from the host system. The default bank address is ‘0’. Commands are provided to load and read the bank address register. These devices may also be configured to take a 4-byte address from the host system with the traditional 3-byte address commands. The 4-byte address mode for traditional commands is activated by setting the External Address (EXTADD) bit in the bank address register to ‘1’. In the FL128S, higher order address bits above A23 in the 4-byte address commands, commands using Extended Address mode, and the Bank Address Register are not relevant and are ignored because the flash array is only 128 Mb in size.
The Quad I/O commands provide a performance improvement option controlled by mode bits that are sent following the address bits. The mode bits indicate whether the command following the end of the current read will be another read of the same type, without an instruction at the beginning of the read. These mode bits give the option to eliminate the instruction cycles when doing a series of Quad I/O read accesses.
A device ordering option provides an enhanced high performance option by adding a similar mode bit scheme to the DDR Fast Read, Dual I/O, and Dual I/O DDR commands, in addition to the Quad I/O command.
Some commands require delay cycles following the address or mode bits to allow time to access the memory array. The delay cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory thus any data provided by the host during these cycles is “don’t care” and the host may also leave the SI signal at high impedance during the dummy cycles. When MIO commands are used the host must stop driving the IO signals (outputs are high impedance) before the end of last dummy cycle. When DDR commands are used the host must not drive the I/O signals during any dummy cycle. The number of dummy cycles varies with the SCK frequency or performance option selected via the Configuration Register 1 (CR1) Latency Code (LC). Dummy cycles are measured from SCK falling edge to next SCK falling edge. SPI outputs are traditionally driven to a new value on the falling edge of each SCK. Zero dummy cycles means the returning data is driven by the memory on the same falling edge of SCK that the host stops driving address or mode bits.
The DDR commands may optionally have an 8-edge Data Learning Pattern (DLP) driven by the memory, on all data outputs, in the dummy cycles immediately before the start of data. The DLP can help the host memory controller determine the phase shift from SCK to data edges so that the memory controller can capture data at the center of the data eye.
When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides ‘1’ or more dummy cycles should be selected to allow additional time for the host to stop driving before the memory starts driving data, to minimize I/O driver conflict. When using DDR I/O commands with the DLP enabled, an LC that provides 5 or more dummy cycles should be selected to allow ‘1’ cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP.
Each read command ends when CS# is returned HIGH at any point during data return. CS# must not be returned HIGH during the mode or dummy cycles before data returns as this may cause mode bits to be captured incor- rectly; making it indeterminate as to whether the device remains in enhanced high performance read mode.
The instruction
03h (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
03h (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
13h is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, are shifted out on SO. The maximum operating clock frequency for the READ command is 50 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely.
SI
24-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CS #
23 22 21
3 2 1 0
SO
High Impedance
DATA OUT 1 DATA OUT 2
7 6 5 4 3 2 1 0 7
MSb MSb
Figure 67 Read command sequence (3-byte address, 03h [ExtAdd = 0])
SI
32-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
CS#
31 30 29
3 2 1 0
SO
High Impedance
DATA OUT 1 DATA OUT 2
7 6 5 4 3 2 1 0 7
MSb MSb
Figure 68 Read command sequence (4-byte address, 13h or 03h [ExtAdd = 1])
The instruction
0Bh (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
0Bh (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
0Ch is followed by a 4-byte address (A31-A0)
The address is followed by zero or eight dummy cycles depending on the latency code set in the Configuration Register. The dummy cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data value on SO is “don’t care” and may be high impedance. Then the memory contents, at the address given, are shifted out on SO.
The maximum operating clock frequency for FAST READ command is 133 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely.
CS#
1 0 7
MSb
SO High Impedance 7
MSb
DATA OUT 2
DATA OUT 1
6 5 4 3 2
3 2 1 0 7 6 5 4 3 2 1 0
23 22 21
SI
Dummy Byte
24-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Figure 69 Fast Read (FAST_READ) command sequence (3-byte address, 0Bh [ExtAdd = 0, LC = 10b])
DATA OUT 1
6 5 4 3 2
31 30 29 3 2 1 0 7 6 5 4 3 2 1 0
SI
Dummy Byte
32-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CS #
DATA OUT 2
SO High Impedance 7
MSb
1 0 7
MSb
Figure 70 Fast Read command sequence (4-byte Address, 0Ch or 0B [ExtAdd=1], LC=10b)
CS#
0 1 2 3 4 5 6 7 8
38 39 40 41 42 43 44 45 46 47 48 49
SCK
Instruction
32 Bit Address
Data 1
Data 2
SI 7 6 5 4 3 2 1 0 31 1 0
SO 7 6 5 4 3 2 1 0 7 6
Figure 71 Fast Read command sequence (4-byte address, 0Ch or 0B [ExtAdd = 1], LC = 11b)
The instruction
3Bh (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
3Bh (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
3Ch is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency by the falling edge of the SCK signal.
The maximum operating clock frequency for the Dual Output Read command is 104 MHz. For Dual Output Read commands, there are zero or eight dummy cycles required after the last address bit is shifted into SI before data begins shifting out of IO0 and IO1. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to read from the initial address. During the dummy cycles, the data value on SI is a “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of SCK (see Table 28).
CS#
SCK
IO0 IO1
Phase
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely.
3
6
5
4
3
2
1
0
23
22
21
0
7
5
1
7
5
3
0
1
7
6
2
4
6
0
2
4
Instruction |
Address | 8 Dummy Cycles | Data 1 | Data 2 |
Figure 72 Dual Output Read command sequence (3-byte address, 3Bh [ExtAdd = 0], LC = 10b)
7 6 5 4 3 2 1 0 31 30 29 0
6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1
Instruction |
Address | 8 Dummy Cycles | Data 1 | Data 2 |
CS#
SCK
IO0 IO1
Phase
CS#
SCK
IO0 IO1
Phase
Figure 73 Dual Output Read command sequence (4-byte address, 3Ch or 3Bh [ExtAdd = 1, LC = 10b])
7 6 5 4 3 2 1 0 31 30 29 0 6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1
Instruction |
Address | Data 1 | Data 2 |
Figure 74 Dual Output Read command sequence (4-byte address, 3Ch or 3Bh [ExtAdd = 1, LC = 11b])
The instruction
6Bh (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
6Bh (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
6Ch is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, is shifted out four bits at a time through IO0-IO3. Each nibble (4-bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The maximum operating clock frequency for Quad Output Read command is 104 MHz. For Quad Output Read mode, there may be dummy cycles required after the last address bit is shifted into SI before data begins shifting out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to set up for the initial address. During the dummy cycles, the data value on IO0-IO3 is a “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of SCK (see Table 28).
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely.
The QUAD bit of Configuration Register must be set (CR Bit1=1) to enable the Quad mode capability.
7 3 7 3
IO3
6 2 6 2
IO2
5 1 5 1
IO1
IO0 7 6 5 4 3 2 1 0 23 1 0 4 0 4 0
Data 1 Data 2
8 Dummy Cycles
24 Bit Address
Instruction
SCK
30 31 32 33 34 35 36 37 38 39 40 41 42 43
0 1 2 3 4 5 6 7 8
CS#
Figure 75 Quad Output Read command sequence (3-byte address, 6Bh [ExtAdd = 0, LC = 01b])
7 3 7 3
IO3
6 2 6 2
IO2
5 1 5 1
IO1
IO0 7 6 5 4 3 2 1 0 31 1 0 4 0 4 0
Data 1 Data 2
8 Dummy Cycles
32 Bit Address
Instruction
SCK
38 39 40 41 42 43 44 45 46 47 48 49 50 51
0 1 2 3 4 5 6 7 8
CS#
Figure 76 Quad Output Read command sequence (4-byte address, 6Ch or 6Bh [ExtAdd = 1, LC = 01b])
7 3 7 3 7 3 7 3
IO3
6 2 6 2 6 2 6 2
IO2
5 1 5 1 5 1 5 1
IO1
1 0 4 0 4 0 4 0 4 0
7 6 5 4 3 2 1 0 31
IO0
Data 1 Data 2 Data 3 Data 3
32 Bit Address
Instruction
SCK
38 39 40 41 42 43 44 45 46 47
0 1 2 3 4 5 6 7 8
CS#
Figure 77 Quad Output Read command sequence (4-byte address, 6Ch or 6Bh [ExtAdd = 1], LC = 11b)
The instruction
BBh (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
BBh (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
BCh is followed by a 4-byte address (A31-A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar to the Dual Output Read command but takes input of the address two bits per SCK rising edge. In some applications, the reduced address input time might allow for code execution in place (XIP) i.e. directly from the memory device.
The maximum operating clock frequency for Dual I/O Read is 104 MHz.
For the Dual I/O Read command, there is a latency required after the last address bits are shifted into SI and SO before data begins shifting out of IO0 and IO1. There are different ordering part numbers that select the latency code table used for this command, either the High Performance LC (HPLC) table (see Table 26) or the Enhanced High Performance LC (EHPLC) table (see Table 28). The HPLC table does not provide cycles for mode bits so each Dual I/O Read command starts with the 8 bit instruction, followed by address, followed by a latency period.
This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. During the dummy cycles, the data value on SI and SO are “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of SCK (see Table 28). The number of dummy cycles is set by the LC bits in the Configuration Register (CR1).
The EHPLC table does provide cycles for mode bits so a series of Dual I/O Read commands may eliminate the 8-bit instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the following command will also be a Dual I/O Read command. The first Dual I/O Read command in a series starts with the 8-bit instruction, followed by address, followed by four cycles of mode bits, followed by a latency period. If the mode bit pattern is Axh the next command is assumed to be an additional Dual I/O Read command that does not provide instruction bits. That command starts with address, followed by mode bits, followed by latency.
The Enhanced High Performance feature removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual I/O Read command through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are “don’t care” (“x”) and may be high impedance. If the Mode bits equal Axh, then the device remains in Dual I/O Enhanced High Performance Read Mode and the next address can be entered (after CS# is raised high and then asserted LOW) without the BBh or BCh instruction, as shown in Figure 81; thus, eliminating eight cycles for the command sequence. The following sequence will release the device from Dual I/O Enhanced High Perfor- mance Read mode; after which, the device can accept standard SPI commands:
During the Dual I/O Enhanced High Performance Command Sequence, if the Mode bits are any value other than Axh, then the next time CS# is raised HIGH the device will be released from Dual I/O Read Enhanced High Perfor- mance Read mode.
During any operation, if CS# toggles HIGH to LOW to high for eight cycles (or less) and data input (IO0 and IO1) are not set for a valid instruction sequence, then the device will be released from Dual I/O Enhanced High Perfor- mance Read mode. Note that the four mode bit cycles are part of the device’s internal circuitry latency time to access the initial address after the last address cycle that is clocked into IO0 (SI) and IO1 (SO).
It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing I/O signal contention, for the host system to turn off the I/O signal outputs (make them high impedance) during the last two “don’t care” mode cycles or during any dummy cycles.
Following the latency period the memory content, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely.
1
19
6
0
18
20
22
5
1
2
3
4
5
3
0
1
7
7
4
2
6
0
6
4
2
1
21
5
3
7
CS#
SCK
IO0 IO1
Phase
23
0
CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate.
Instruction |
Address | 4 Dummy | Data 1 | Data 2 |
26
0
27
1
CS#
SCK
IO0 IO1
Phase
0
1
28
4
6
0
2
4
6
31
2
29
7
5
4
3
6
0
1
30
2
7
3
5
7
1
3
5
Figure 78 Dual I/O Read command sequence (3-byte address, BBh [ExtAdd = 0], HPLC = 00b)
Instruction |
Address | 6 Dummy | Data 1 | Data 2 |
Figure 79 Dual I/O Read command sequence (4-byte address, BBh [ExtAdd = 1], HPLC = 10b)
7 5 3 1 7 5 3
3 1
5
3 1 7
31
IO1
6 4 2 0 6 4 2
2 0
4
2 0 6
IO0 7 6 5 4 3 2 1 0 30
Data 2
4 cycles
Data 1
2 cycles
Dummy
4 cycles
Mode
16 cycles
32 Bit Address
8 cycles
Instruction
SCK
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
0 1 2 3 4 5 6 7 8
CS#
Figure 80 Dual I/O Read command sequence (4-byte address, BCh or BBh [ExtAdd = 1], EHPLC = 10b)
7 5 3 1
IO0
IO1
31
3 1 7
5
3 1
7 5 3 1 7 5 3 1
CS#
SCK
6 4 2 0 6 4 2 0
2 0
4
2 0 6
30
6 4 2 0
4 cycles
Data 2
4 cycles
Data 1
2 cycles
Dummy
4 cycles
Mode
16 cycles
32 Bit Address
4 cycles
Data N
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
0
Figure 81 Continuous Dual I/O Read command sequence (4-byte address, BCh or BBh [ExtAdd = 1], EHPLC = 10b)
The instruction
EBh (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
EBh (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
ECh is followed by a 4-byte address (A31-A0)
The Quad I/O Read command improves throughput with four I/O signals — IO0-IO3. It is similar to the Quad Output Read command but allows input of the address bits four bits per serial SCK clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly from S25FL128S and S25FL256S devices. The QUAD bit of the Configuration Register must be set (CR Bit1=1) to enable the Quad capability of S25FL128S and S25FL256S devices.
The maximum operating clock frequency for Quad I/O Read is 104 MHz.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before data begins shifting out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to access data at the initial address. During latency cycles, the data value on IO0-IO3 are “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of SCK and the latency code table (see Table 28). There are different ordering part numbers that select the latency code table used for this command, either the High Performance LC (HPLC) table (see Table 26) or the Enhanced High Performance LC (EHPLC) table (see Table 28). The number of dummy cycles is set by the LC bits in the Configuration Register (CR1). However, both latency code tables use the same latency values for the Quad I/O Read command.
Following the latency period, the memory contents at the address given, is shifted out four bits at a time through IO0-IO3. Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely.
Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through the setting of the Mode bits (after the address sequence, as shown in Figure 82 or Figure 84). This added feature removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are “don’t care” (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O High Performance Read Mode and the next address can be entered (after CS# is raised HIGH and then asserted LOW) without requiring the EBh or ECh instruction, as shown in Figure 83 or Figure 85; thus, eliminating eight cycles for the command sequence. The following sequence will release the device from Quad I/O High Performance Read mode; after which, the device can accept standard SPI commands:
During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh, then the next time CS# is raised HIGH the device will be released from Quad I/O High Performance Read mode.
During any operation, if CS# toggles HIGH to LOW to HIGH for eight cycles (or less) and data input (IO0-IO3) are not set for a valid instruction sequence, then the device will be released from Quad I/O High Performance Read mode. Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device’s internal circuitry latency time to access the initial address after the last address cycle that is clocked into IO0-IO3.
It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data out clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing IO0-IO3 signal contention, for the host system to turn off the IO0-IO3 signal outputs (make them high impedance) during the last “don’t care” mode cycle or during any dummy cycles.
CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate.
5 1
7 3 7 1
5
1
5 1 5 1
IO2
22
6 2
6
2
6 2 6 1
IO3
23
7 3
7
3
21
IO1
4 0 4 0
0
4
4 0
IO0 7 6 5 4 3 2 1 0 20
2 cycles
Data 1 Data 2
4 cycles
Dummy
2 cycles
Mode
6 cycles
24 Bit Address
8 cycles
Instruction
SCK
12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8
CS#
Figure 82 Quad I/O Read command sequence (3-byte address, EBh [ExtAdd = 0], LC = 00b)
5 1
7 3 7 1
5
1
5 1 5 1
IO2 6 2 6 2
22
6 2
6
2
6 2 6 1
IO3 7 3 7 3
23
7 3
7
3
2 cycles 2 cycles
Data 1 Data 2
CS#
0
4 5 6 7 8 9 10 11 12 13 14
SCK
2 cycles 2 cycles
Data N Data N+1
6 cycles
24 Bit Address
2 cycles
Mode
4 cycles
Dummy
21
IO0 4 0 4 0
20
4 0
4
0
4 0 4 0
IO1 5 1 5 1
Figure 83 Continuous Quad I/O Read command sequence (3-byte address), LC = 00b
2
5
1
5 1 5 1
IO2
30
6 2
6
29
6 2 6 1
IO3
31
7 3
7
3
7 3 7 1
5 1
IO1
4 0 4 0
0
4
4 0
IO0 7 6 5 4 3 2 1 0 28
2 cycles
Data 1 Data 2
4 cycles
Dummy
2 cycles
Mode
8 cycles
32 Bit Address
8 cycles
Instruction
SCK
14 15 16 17 18 19 20 21 22 23 24 25
0 1 2 3 4 5 6 7 8
CS#
Figure 84 Quad I/O Read command sequence(4-byte address, ECh or EBh [ExtAdd = 1], LC = 00b)
7 3
7
31
IO3 7 3 7 3
6 2 6 1
2
6
6 2
30
IO2 6 2 6 2
5 1 5 1
1
5
7 3 7 1
5 1
2 cycles
Mode
4 0 4 0
0
4
4 0
28
IO0 4 0 4 0
29
4 cycles
Dummy
IO1 5 1 5 1
8 cycles
32 Bit Address
2 cycles 2 cycles
Data N Data N+1
SCK
6 7 8 9 10 11 12 13 14 15 16
0
CS#
2 cycles 2 cycles
Data 1 Data 2
3
Figure 85 Continuous Quad I/O Read command sequence (4-byte address), LC = 00b
The instruction
0Dh (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
0Dh (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
0Eh is followed by a 4-byte address (A31-A0)
The DDR Fast Read command improves throughput by transferring address and data on both the falling and rising edge of SCK. It is similar to the Fast Read command but allows transfer of address and data on every edge of the clock.
The maximum operating clock frequency for DDR Fast Read command is 80 MHz.
For the DDR Fast Read command, there is a latency required after the last address bits are shifted into SI before data begins shifting out of SO. There are different ordering part numbers that select the latency code table used for this command, either the High Performance LC (HPLC) table (see Table 27) or the Enhanced High Perfor- mance LC (EHPLC) table (see Table 29). The HPLC table does not provide cycles for mode bits so each DDR Fast Read command starts with the 8 bit instruction, followed by address, followed by a latency period.
This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. During the dummy cycles, the data value on SI is “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of SCK (Table 28). The number of dummy cycles is set by the LC bits in the Configuration Register (CR1).
Then the memory contents, at the address given, is shifted out, in DDR fashion, one bit at a time on each clock edge through SO. Each bit is shifted out at the SCK frequency by the rising and falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely.
The EHPLC table does provide cycles for mode bits so a series of DDR Fast Read commands may eliminate the 8-bit instruction after the first DDR Fast Read command sends a mode bit pattern of complementary first and second Nibbles, e.g., A5h, 5Ah, 0Fh, etc., that indicates the following command will also be a DDR Fast Read command. The first DDR Fast Read command in a series starts with the 8-bit instruction, followed by address,
followed by four cycles of mode bits, followed by a latency period. If the mode bit pattern is complementary the next command is assumed to be an additional DDR Fast Read command that does not provide instruction bits. That command starts with address, followed by mode bits, followed by latency.
When the EHPLC table is used, address jumps can be done without the need for additional DDR Fast Read instruc- tions. This is controlled through the setting of the Mode bits (after the address sequence, as shown in Figure 86 and Figure 88. This added feature removes the need for the eight bit SDR instruction sequence to reduce initial access time (improves XIP performance). The Mode bits control the length of the next DDR Fast Read operation through the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e., 5h and Ah) then the next address can be entered (after CS# is raised HIGH and then asserted LOW) without requiring the 0Dh or 0Eh instruction, as shown in Figure 87 and Figure 89, thus, eliminating eight cycles from the command sequence. The following sequences will release the device from this continuous DDR Fast Read mode; after which, the device can accept standard SPI commands:
During the DDR Fast Read command sequence, if the Mode bits are not complementary the next time CS# is raised HIGH the device will be released from the continuous DDR Fast Read mode.
During any operation, if CS# toggles HIGH to LOW to HIGH for eight cycles (or less) and data input (SI) are not set for a valid instruction sequence, then the device will be released from DDR Fast Read mode.
CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate. The HOLD function is not valid during any part of a Fast DDR Command.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four IOs on a x4 device, both IOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover both DC and AC data transition scenarios. The two DC transition scenarios include data low for a long period of time (two half clocks) followed by a high going transition (001) and the complementary low going transition (110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by a high going transition (101) and the complementary low going transition (010). The DC transitions will typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been characterized the optimal data capture point can be chosen. See “SPI DDR Data Learning Registers” on page 60 for more details.
IO0 7 6 5 4 3 2 1 0 2 2 1 0 7 6 5 4 3 2 1 0
IO1 7 6 5 4 3 2 1 0 7 6
4 cycles
per data
1 cyc
Dummy
4 cycles
Mode
12 cycles
24 Bit Address
8 cycles
Instruction
SCK
0 1 2 3 4 5 6 7 8 19 20 21 22 23 24 25 26 27 28 29
CS#
Figure 86 DDR Fast Read initial access (3-byte address, 0Dh [ExtAdd = 0, EHPLC = 11b])
19
7 6 5 4 3 2 1 0 7 6
IO1
23 22 1 0 7 6 5 4 3 2 1 0
IO0
4 cycles
per data
1 cyc
Dummy
4 cycles
Mode
12 cycles
24 Bit Address
SCK
21
20
18
17
16
15
14
13
12
11
0
CS#
Figure 87 Continuous DDR Fast read subsequent access (3-byte address [ExtAdd = 0, EHPLC = 11b])
7 6
1 0
5 4 3 2
7 6
1 0
5 4 3 2
7 6
SO
1 0
2
5 4 3
7 6
31 22 1 0
0
1
2
3
4
5
6
SI 7
4 cycles per data
4 cycles Dummy Optional DLP
4 cycles Mode
16 cycles 32b Add
8 cycles Instruction
SCK
0 1 2 3 4 5 6 7 8 23 24 25 26 27 28 29 30 31 32 33 34 35 36
CS#
Figure 88 DDR Fast Read initial access (4-byte address, 0Eh or 0Dh [ExtAdd = 1], EHPLC = 01b)[54]
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
SO
31 22 1 0 7 6 5 4 3 2 1 0
SI
4 cycles
per data
4 cycles Dummy
Optional DLP
4 cycles
Mode
16 cycles
32b Add
SCK
28
27
26
25
24
22 23
21
20
19
18
17
16
15
0
CS#
Figure 89 Continuous DDR Fast Read subsequent access (4-byte address [ExtAdd = 1], EHPLC = 01b)[54]
CS#
0 1 2 3 4 5 6 7 8 23 24 25 26 27 28 29 30 31 32 33 34
SCK
8 cycles
Instruction
16 cycles
32b Add
6 cycles
Dummy
4 cycles
per data
SI
7 6 5 4 3 2 1 0 31 22 1 0
SO
7 6 5 4 3 2 1 0 7 6
Figure 90 DDR Fast Read subsequent access (4-byte address, HPLC = 01b)
Note
Example DLP of 34h (or 00110100).
The instruction
BDh (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
BDh (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
BEh is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, is shifted out, in a DDR fashion, two bits at a time on each clock edge through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency by the rising and falling edge of the SCK signal.
The DDR Dual I/O Read command improves throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar to the Dual I/O Read command but transfers two address, mode, or data bits on every edge of the clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly from S25FL128S and S25FL256S devices.
The maximum operating clock frequency for DDR Dual I/O Read command is 80 MHz.
For DDR Dual I/O Read commands, there is a latency required after the last address bits are shifted into IO0 and IO1, before data begins shifting out of IO0 and IO1. There are different ordering part numbers that select the latency code table used for this command, either the High Performance LC (HPLC) table (see Table 27) or the Enhanced High Performance LC (EHPLC) table (see Table 29). The number of latency (dummy) clocks is deter- mined by the frequency of SCK (see Table 27 or Table 29). The number of dummy cycles is set by the LC bits in the Configuration Register (CR1).
The HPLC table does not provide cycles for mode bits so each Dual I/O command starts with the 8 bit instruction, followed by address, followed by a latency period. This latency period allows the device’s internal circuitry enough time to access the initial address. During these latency cycles, the data value on SI (IO0) and SO (IO1) are “don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must be left high impedance by the host so that the memory device can drive the DLP during the dummy cycles.
The EHPLC table does provide cycles for mode bits so a series of Dual I/O DDR commands may eliminate the 8-bit instruction after the first command sends a complementary mode bit pattern, as shown in Figure 91 and Figure 93. This added feature removes the need for the eight bit SDR instruction sequence and dramatically reduces initial access times (improves XIP performance). The Mode bits control the length of the next DDR Dual I/O Read operation through the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e., 5h and Ah) the device transitions to Continuous DDR Dual I/O Read Mode and the next address can be entered (after CS# is raised HIGH and then asserted LOW) without requiring the BDh or BEh instruction, as shown in Figure 92, and thus, eliminating eight cycles from the command sequence. The following sequences will release the device from Continuous DDR Dual I/O Read mode; after which, the device can accept standard SPI commands:
During the DDR Dual I/O Read command Sequence, if the Mode bits are not complementary the next time CS# is raised HIGH and then asserted LOW the device will be released from DDR Dual I/O Read mode.
During any operation, if CS# toggles HIGH to LOW to HIGH for eight cycles (or less) and data input (IO0 and IO1) are not set for a valid instruction sequence, then the device will be released from DDR Dual I/O Read mode.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely.
CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate. The HOLD function is not valid during Dual I/O DDR commands.
Note that the memory devices may drive the IOs with a preamble prior to the first data value. The preamble is a data learning pattern (DLP) that is used by the host controller to optimize data capture at higher frequencies. The preamble DLP drives the IO bus for the four clock cycles immediately before data is output. The host must be sure to stop driving the IO bus prior to the time that the memory starts outputting the preamble.
The preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to when the corresponding data value returns from the memory device. The host controller will skew the data capture point during the preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read operation. The optimized capture point will be deter- mined during the preamble period of every read operation. This optimization strategy is intended to compensate for both the PVT (process, voltage, temperature) of both the memory device and the host controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four SIOs on a x4 device, both SIOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover both DC and AC data transition scenarios. The two DC transition scenarios include data low for a long period of time (two half clocks) followed by a high going transition (001) and the complementary low going transition (110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by a high going transition
(101) and the complementary low going transition (010). The DC transitions will typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been characterized the optimal data capture point can be chosen. See “SPI DDR Data Learning Registers” on page 60 for more details.
30 22 2
2 1 0 7 5 3 1 7
0
6 4 2
0
7 6 5 4 3
2
1 0
6 4 2 0
6
IO1
31 22 3
1 7 5 3
1
7 6 5 4 3
0
1
2
3
4
5
6
IO0 7
2 cycles per data
5 cycles Dummy Optional DLP
2 cycles Mode
8 cycles 32b Add
8 cycles Instruction
SCK
0 1 2 3 4 5 6 7 8 15 16 17 18 19 20 21 22 23 24 25
CS#
Figure 91 DDR Dual I/O Read initial access (4-byte address, BEh or BDh [ExtAdd = 1], EHPLC = 01b)
7 6 5 4 3 2 1 0 7 5 3 1 7
31 22 3 1 7 5 3 1
IO1
7 6 5 4 3 2 1 0 6 4 2 0 6
30 22 2 0 6 4 2 0
IO0
2 cycles
per data
5 cycles Dummy
Optional DLP
2 cycles
Mode
8 cycles
32b Add
SCK
17
16
15
8
14
13
12
11
10
9
8
0
CS#
Figure 92 Continuous DDR Dual I/O Read subsequent access (4-byte address, EHPLC = 01b)
CS#
0
1
2
3
4
5
6
7
8 15 16 17 18 19 20 21 22 23 24
SCK
8 cycles
Instruction
8 cycles
32b Add
6 cycles
Dummy
2 cycles
per data
IO0
7
6
5
4
3
2
1
0 30 2 0
6 4 2 0 6
IO1
31
3 1
7 5 3 1 7 2
Figure 93 DDR Dual I/O Read (4-byte address, BEh or BDh [ExtAdd = 1], HPLC = 00b)
The Read DDR Quad I/O command improves throughput with four I/O signals - IO0-IO3. It is similar to the Quad I/O Read command but allows input of the address four bits on every edge of the clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly from S25FL128S and S25FL256S devices. The QUAD bit of the Configuration Register must be set (CR Bit1=1) to enable the Quad capability.
The instruction
EDh (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
EDh (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
EEh is followed by a 4-byte address (A31-A0)
The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a DDR fashion, with four bits at a time on each clock edge through IO0-IO3.
The maximum operating clock frequency for Read DDR Quad I/O command is 80 MHz.
For Read DDR Quad I/O, there is a latency required after the last address and mode bits are shifted into the IO0-IO3 signals before data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the device’s internal circuitry enough time to access the initial address. During these latency cycles, the data value on IO0-IO3 are “don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must be left high impedance by the host so that the memory device can drive the DLP during the dummy cycles.
There are different ordering part numbers that select the latency code table used for this command, either the High Performance LC (HPLC) table (see Table 27) or the Enhanced High Performance LC (EHPLC) table (see Table 29). The number of dummy cycles is determined by the frequency of SCK (see Table 27). The number of dummy cycles is set by the LC bits in the Configuration Register (CR1).
Both latency tables provide cycles for mode bits so a series of Quad I/O DDR commands may eliminate the 8 bit instruction after the first command sends a complementary mode bit pattern, as shown in Figure 94 and Figure 96. This feature removes the need for the eight bit SDR instruction sequence and dramatically reduces initial access times (improves XIP performance). The Mode bits control the length of the next Read DDR Quad I/O operation through the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e., 5h and Ah) the device transitions to Continuous Read DDR Quad I/O Mode and the next address can be entered (after CS# is raised HIGH and then asserted LOW) without requiring the EDh or EEh instruction, as shown in Figure 95 and Figure 97 thus, eliminating eight cycles from the command sequence. The following sequences will release the device from Continuous Read DDR Quad I/O mode; after which, the device can accept standard SPI commands:
During the Read DDR Quad I/O Command Sequence, if the Mode bits are not complementary the next time CS# is raised HIGH and then asserted LOW the device will be released from Read DDR Quad I/O mode.
During any operation, if CS# toggles HIGH to LOW to HIGH for eight cycles (or less) and data input (IO0, IO1, IO2, and IO3) are not set for a valid instruction sequence, then the device will be released from Read DDR Quad I/O mode.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely.
CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate. The HOLD function is not valid during Quad I/O DDR commands.
Note that the memory devices drive the IOs with a preamble prior to the first data value. The preamble is a pattern that is used by the host controller to optimize data capture at higher frequencies. The preamble drives the IO bus for the four clock cycles immediately before data is output. The host must be sure to stop driving the IO bus prior to the time that the memory starts outputting the preamble.
The preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to when the corresponding data value returns from the memory device. The host controller will skew the data capture point during the preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read operation. The optimized capture point will be deter- mined during the preamble period of every read operation. This optimization strategy is intended to compensate for both the PVT (process, voltage, temperature) of both the memory device and the host controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four SIOs on a x4 device, both SIOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover both DC and AC data transition scenarios. The two DC transition scenarios include data low for a long period of time (two half clocks) followed by a high going transition (001) and the complementary low going transition (110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by a high going transition
(101) and the complementary low going transition (010). The DC transitions will typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been characterized the optimal data capture point can be chosen. See “SPI DDR Data Learning Registers” on page 60 for more details.
6 2 6 2
IO3
22 18 14 10 6 2 6 2
IO2
5 1 5 1
21 17 13 9 5 1 5 1
IO1
4 0 4 0
0 20 16 12 8 4 0 4 0
1
2
3
4
5
6
7
IO0
Data 1
7 3 7 3
Data 0
7
1 cycle
Mode
3 cycles
Address
8 cycles
Instruction
SCK
16
15
12 13 14
11
10
1 cycle per data
8
3 cycle Dummy
High-Z Bus Turn-around
6
5
4
3
2
1
0
CS#
9
23 19 15 11 7 3 7 3
Figure 94 DDR Quad I/O Read initial access (3-byte address, EDh [ExtAdd = 0], HPLC = 11b)
3
7
2
6
2
6
2
IO3
23 19 15 11 7
3
7
3
3
5
1
5
1
5
1
5
1
IO2
22 18 14 10 6
2
21 17 13 9
6
3 cycle
Address
4
0
4
0
4
0
4
20 16 12 8
IO0
Data 1
Data 0
1 cycle per data
IO1
1 cycle
Mode
0
SCK
8
7
6
5
4
3
2
1
0
CS#
3 cycle Dummy
High-Z Bus Turn-around
7
Figure 95 Continuous DDR Quad I/O Read subsequent access (3-byte address, HPLC = 11b)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
SCK
8 cycles Instruction
4 cycles
32 Bit Address
1 cycle Mode
7 cycle Dummy 1 cycle per data
High-Z Bus Turn-around Optional Data Learning Pattern
Data 0
Data 1
IO0
7 6 5 4 3 2 1 0 28 24 20 16 12 8 4 0 4 0
7 6 5 4 3 2 1 0 4 0 4 0
IO1 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1
IO2 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2
IO3 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3
Figure 96 DDR Quad I/O Read initial access (4-byte address, EEh or EDh [ExtAdd = 1], EHPLC = 01b)[55]
7 6 5 4 3 2 1 0 7 3 7 3
31 27 23 19 15 11 7 3 7 3
IO3
7 6 5 4 3 2 1 0 6 2 6 2
30 26 22 18 14 10 6 2 6 2
IO2
7 6 5 4 3 2 1 0 5 1 5 1
29 25 21 17 13 9 5 1 5 1
IO1
7 6 5 4 3 2 1 0 4 0 4 0
28 24 20 16 12 8 4 0 4 0
IO0
Data 1
Data 0
1 cycle per data
7 cycle Dummy
Optional Data Learning Pattern
1 cycle
Mode High-Z Bus Turn-around
4 cycles
32 Bit Address
SCK
10 11 12 13
7 8 9
6
5
4
3
2
1
0
CS#
Figure 97 Continuous DDR Quad I/O Read subsequent access (4-byte address, EHPLC = 01b)[56]
Each 16-byte aligned and 16-byte length Programming Block has an automatic Error Correction Code (ECC) value. The data block plus ECC form an ECC unit. In combination with Error Detection and Correction (EDC) logic the ECC is used to detect and correct any single bit error found during a read access. When data is first programmed within an ECC unit the ECC value is set for the entire ECC unit. If the same ECC unit is programmed more than once the ECC value is changed to disable the Error Detection and Correction (EDC) function. A sector erase is needed to again enable Automatic ECC on that Programming Block. The 16 byte Program Block is the smallest program granularity on which Automatic ECC is enabled.
These are automatic operations transparent to the user. The transparency of the Automatic ECC feature enhances data accuracy for typical programming operations which write data once to each ECC unit but, facili- tates software compatibility to previous generations of FL-S family of products by allowing for single byte programming and bit walking in which the same ECC unit is programmed more than once. When an ECC unit has Automatic ECC disabled, EDC is not done on data read from the ECC unit location.
An ECC status register is provided for determining if ECC is enabled on an ECC unit and whether any errors have been detected and corrected in the ECC unit data or the ECC (See “ECC Status Register (ECCSR)” on page 58.) The ECC Status Register Read (ECCRD) command is used to read the ECC status on any ECC unit.
EDC is applied to all parts of the Flash address spaces other than registers. An ECC is calculated for each group of bytes protected and the ECC is stored in a hidden area related to the group of bytes. The group of protected bytes and the related ECC are together called an ECC unit.
ECC is calculated for each 16 byte aligned and length ECC unit.
Note
Example DLP of 34h (or 00110100).
Example DLP of 34h (or 00110100).
Single Bit EDC is supported with 8 ECC bits per ECC unit, plus ‘1’ bit for an ECC disable Flag.
Sector erase resets all ECC bits and ECC disable flags in a sector to the default state (enabled).
ECC is programmed as part of the standard Program commands operation.
ECC is disabled automatically if multiple programming operations are done on the same ECC unit.
Single byte programming or bit walking is allowed but disables ECC on the second program to the same 16-byte ECC unit.
The ECC disable flag is programmed when ECC is disabled.
To re-enable ECC for an ECC unit that has been disabled, the Sector that includes the ECC unit must be erased.
To ensure the best data integrity provided by EDC, each ECC unit should be programmed only once so that ECC is stored for that unit and not disabled.
The calculation, programming, and disabling of ECC is done automatically as part of a programming operation. The detection and correction, if needed, is done automatically as part of read operations. The host system sees only corrected data from a read operation.
ECC protects the OTP region - however a second program operation on the same ECC unit will disable ECC permanently on that ECC unit (OTP is one time programmable, hence an erase operation to re-enable the ECC enable/indicator bit is prohibited).
Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming command to move data from the buffer to the memory array. This sets an upper limit on the amount of data that can be programmed with a single programming command. Page Programming allows up to a page size (either 256- or 512-bytes) to be programmed in one operation. The page size is determined by the Ordering Part Number (OPN). The page is aligned on the page size address boundary. It is possible to program from one bit up to a page size in each Page programming operation. It is recommended that a multiple of 16-byte length and aligned Program Blocks be written. For the very best performance, programming should be done in full pages of
512-bytes aligned on 512-byte boundaries with each Page being programmed only once.
Single Byte Programming allows full backward compatibility to the standard SPI Page Programming (PP) command by allowing a single byte to be programmed anywhere in the memory array. While single byte programming is supported, this will disable Automatic ECC on the 16 byte ECC unit where the byte is located.
The Page Program (PP) commands allows bytes to be programmed in the memory (changing bits from 1 to 0). Before the Page Program (PP) commands can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
02h (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
02h (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
12h is followed by a 4-byte address (A31-A0)
and at least one data byte on SI. Depending on the device OPN, the page size can either be 256 or 512 bytes. Up to a page can be provided on SI after the 3-byte address with instruction 02h or 4-byte address with instruction 12h has been provided. If the 9 least significant address bits (A8-A0) are not all ‘0’, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 9 least significant bits (A8-A0) are all ‘0’) i.e., the address wraps within the page aligned address bound- aries. This is a result of only requiring the user to enter one single page address to cover the entire page boundary.
If less than a page of data is sent to the device, these data bytes will be programmed in sequence, starting at the provided address within the page, without having any affect on the other bytes of the same page.
For optimized timings, using the Page Program (PP) command to load the entire page size program buffer within the page boundary will save overall programming time versus loading less than a page size into the program buffer.
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSb MSb MSb
SI
Data Byte 512
Data Byte 3
Data Byte 2
SCK
40 41 42 43 44 45 46 47 48 49 59 51 52 53 54 55
CS#
3 2 1 0 7 6 5 4 3 2 1 0
MSb
23 22 21
MSb
SI
Data Byte 1
24-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CS#
The programming process is managed by the flash memory device internal control logic. After a programming command is issued, the programming operation status can be checked using the Read Status Register-1 command. The WIP bit (SR1[0]) will indicate when the programming operation is completed. The P_ERR bit (SR1[6]) will indicate if an error occurs in the programming operation that prevents successful completion of programming.
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSb MSb MSb
SI
Data Byte 512
Data Byte 3
Data Byte 2
SCK
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
CS#
31 30 29 3 2 1 0 7 6 5 4 3 2 1 0
MSb MSb
SI
Data Byte 1
32-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
CS#
4120
4121
4122
4123
4124
4125
4126
4127
Figure 98 Page Program (PP) command sequence (3-byte address, 02h)
4128
4129
4130
4131
4132
4133
4134
4135
Figure 99 Page Program (4PP) command sequence (4-byte address, 12h)
The Quad-input Page Program (QPP) command allows bytes to be programmed in the memory (changing bits from ‘1’ to ‘0’). The Quad-input Page Program (QPP) command allows up to a page size (either 256- or 512-bytes) of data to be loaded into the Page Buffer using four signals: IO0-IO3. QPP can improve performance for PROM Programmer and applications that have slower clock speeds (< 12 MHz) by loading 4-bits of data per clock cycle. Systems with faster clock speeds do not realize as much benefit for the QPP command since the inherent page program time becomes greater than the time it takes to clock-in the data. The maximum frequency for the QPP command is 80 MHz.
To use Quad Page Program the Quad Enable Bit in the Configuration Register must be set (QUAD=1). A Write Enable command must be executed before the device will accept the QPP command (Status Register 1, WEL=1).
The instruction
32h (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
32h (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
38h (ExtAdd = 0) is followed by a 3-byte address (A23-A0) or
38h (ExtAdd = 1) is followed by a 4-byte address (A31-A0) or
34h is followed by a 4-byte address (A31-A0)
and at least one data byte, into the IO signals. Data must be programmed at previously erased (FFh) memory locations.
The programming page is aligned on the page size address boundary. It is possible to program from one bit up to a page size in each Page programming operation. It is recommended that a multiple of 16-byte length and aligned Program Blocks be written. This insures that Automatic ECC is not disabled.
1
2
Byte 509 Byte 510Byte 511 Byte 512
IO3
7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
* * *
Byte 5
Byte 6
*
Byte 7
*
Byte 8
*
Byte 9 Byte 10 Byte 11 Byte 12
* * * *
7 3
*
*
*MSb
0 4 0 4 0 4 0
1 5 1 56 1 5 1
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Instruction
24-Bit Address
IO0
23 22 21 3 2 1 0 4
IO1 * 5
5
6
IO2 6 2 6 2 6 2 6 2
IO3 7 3 7 3 7 3 7 3
B*yte 1 B*yte 2 B*yte 3 B*yte 4
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
IO0 4 0
IO1 5 1
4 0 4 0 4 0 4 0 4 0 4 0 4 0
5 1 5 1 5 1 5 1 5 1 5 1 5 1
IO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
4 0 4 0 4
5 1 5 1 5
6 2 6 2 6
0
1
2
4 0
All other functions of QPP are identical to Page Program. The QPP command sequence is shown in Figure 100.
536
537
538
539
540
541
542
543
Figure 100 Quad 512-Byte Page Program command sequence (3-byte address, 32h or 38h)
Byte 253 Byte 254Byte 255 Byte 256
*MSb
7 3 7 3
* *
* * * *
Byte 9 Byte 10 Byte 11 Byte 12
*
Byte 8
*
Byte 7
*
Byte 6
*
Byte 5
IO3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
* *
IO1 * 5 1 5 1 56 1 5 1
IO2 6 2 6 2 6 2 6 2
IO3 7 3 7 3 7 3 7 3
B*yte 1 B*yte 2 B*yte 3 B*yte 4
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
IO0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
IO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
IO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
23 22 21 3 2 1 0 4 0 4 0 4 0 4 0
IO0
24-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CS#
Byte Byte Byte Byte
*MSb 509 510 511 512
*
*
*
*
* * * * *
Byte 8 Byte 9 Byte 10 Byte 11 Byte 12
* *
Byte 6 Byte 7
*
Byte 5
CS#
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SCK
IO0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
IO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
IO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
IO3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
7 3 7 3 7 3 7 3
B*yte 1 B*yte 2 B*yte 3 B*yte 4
IO3
0 4 0 4 0 4 0
1 5 1 56 1 5 1
6 2 6 2 6 2 6 2
3 2 1 0 4
5
7 6 5 4 3 2 1 0 31 30 29
* *
IO0
IO1 IO2
32-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
CS#
280
281
282
283
284
285
286
287
Figure 101 Quad 256-byte Page Program command sequence (3-byte address, 32h or 38h)
544
545
546
547
548
549
550
551
Figure 102 Quad 512-byte Page Program command sequence (4-byte address, 34h or 32h or 38h [ExtAdd = 1])
Byte Byte Byte Byte
*MSb 253 254 255 256
*
*
*
*
* * * * *
Byte 8 Byte 9 Byte 10 Byte 11 Byte 12
* *
Byte 6 Byte 7
*
Byte 5
IO3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
5 1 5 1 5 1 5 1
6 2 6 2 6 2 6 2
IO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
IO1 * * 5 1 5 1 56 1 5 1
IO2 6 2 6 2 6 2 6 2
IO3 7 3 7 3 7 3 7 3
B*yte 1 B*yte 2 B*yte 3 B*yte 4
CS#
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SCK
IO0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
IO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
7 6 5 4 3 2 1 0 31 30 29 3 2 1 0 4 0 4 0 4 0 4 0
IO0
32-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
CS#
288
289
290
291
292
293
294
295
Figure 103 Quad 256-byte Page Program command sequence (4-Byte Address, 34h or 32h or 38h [ExtAdd=1])
The Program Suspend command allows the system to interrupt a programming operation and then read from any other non-erase-suspended sector or non-program-suspended-page. Program Suspend is valid only during a programming operation.
Commands allowed after the Program Suspend command is issued:
Read Status Register 1 (RDSR1 05h)
Read Status Register 2 (RDSR2 07h)
The Write in Progress (WIP) bit in Status Register 1 (SR1[0]) must be checked to know when the programming operation has stopped. The Program Suspend Status bit in the Status Register-2 (SR2[0]) can be used to determine if a programming operation has been suspended or was completed at the time WIP changes to ‘0’. The time required for the suspend operation to complete is tPSL, see Table 42.
See Table 52 for the commands allowed while programming is suspend.
The Program Resume command 8Ah must be written to resume the programming operation after a Program Suspend. If the programming operation was completed during the suspend operation, a resume command is not needed and has no effect if issued. Program Resume commands will be ignored unless a Program operation is suspended.
After a Program Resume command is issued, the WIP bit in the Status Register-1 will be set to a ‘1’ and the programming operation will resume. Program operations may be interrupted as often as necessary e.g., a program suspend command could immediately follow a program resume command but, in order for a program operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to tPRS. See Table 42.
0
7
SO
7 6 5
Read Status
0
SI 7 6 5 4 3 2 1 0 7 6
Prog. Suspend Mode Command
Program Suspend Instruction
CS#
SCK
tPSL
tPSL
Figure 104 Program Suspend command sequence
Resume Programming
SO
7 6 5 4 3 2 1 0
MSb
High Impedance
SI
Instruction (8Ah)
SCK
0 1 2 3 4 5 6 7
CS#
Figure 105 Program Resume command sequence
The P4E command is implemented only in FL128S and FL256S. The P4E command is ignored when the device is configured with the 256-KB sector option.
The Parameter 4-KB Sector Erase (P4E) command sets all the bits of a 4-KB parameter sector to ‘1’ (all bytes are FFh). Before the P4E command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
20h [ExtAdd = 0] is followed by a 3-byte address (A23-A0), or
20h [ExtAdd = 1] is followed by a 4-byte address (A31-A0), or
21h is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic HIGH state after the twenty-fourth or thirty-second bit of the address has been latched in on SI. This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of the chosen sector of the flash memory array. If CS# is not driven high after the last bit of address, the sector erase operation will not be executed.
As soon as CS# is driven HIGH, the internal erase cycle will be initiated. With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a ‘1’. when the erase cycle is in progress and a ‘0’ when the erase cycle has been completed.
A P4E command applied to a sector that has been write protected through the Block Protection bits or ASP, will not be executed and will set the E_ERR status. A P4E command applied to a sector that is larger than 4 KB will not be executed and will not set the E_ERR status.
3 2 1 0
23 22 21
MSb
SI
24 Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CS #
Figure 106 Parameter Sector Erase command sequence (3-byte address, 20h)
3 2 1 0
31 30 29
MSb
SI
32 Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39
CS #
Figure 107 Parameter Sector Erase command sequence (ExtAdd = 1, 20h or 4-byte address, 21h)
The Sector Erase (SE) command sets all bits in the addressed sector to ‘1’ (all bytes are FFh). Before the Sector Erase (SE) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write opera- tions.
The instruction
D8h [ExtAdd = 0] is followed by a 3-byte address (A23-A0), or
D8h [ExtAdd = 1] is followed by a 4-byte address (A31-A0), or
DCh is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic HIGH state after the twenty-fourth or thirty-second bit of address has been latched in on SI. This will initiate the erase cycle, which involves the pre-programming and erase of the chosen sector. If CS# is not driven HIGH after the last bit of address, the sector erase operation will not be executed.
As soon as CS# is driven into the logic HIGH state, the internal erase cycle will be initiated. With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the operation has been completed. The WIP bit will indicate a ‘1’ when the erase cycle is in progress and a0 when the erase cycle has been completed.
A Sector Erase (SE) command applied to a sector that has been Write Protected through the Block Protection bits or ASP, will not be executed and will set the E_ERR status.
A device ordering option determines whether the SE command erases 64 KB or 256 KB. The option to use this command to always erase 256 KB provides for software compatibility with higher density and future S25FL family devices.
ASP has a PPB and a DYB protection bit for each sector, including any 4-KB sectors. If a sector erase command is applied to a 64-KB range that includes a protected 4-KB sector, or to a 256-KB range that includes a 64-KB protected address range, the erase will not be executed on the range and will set the E_ERR status.
3 2 1 0
23 22 21
MSb
SI
24 Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CS #
Figure 108 Sector Erase command sequence (ExtAdd = 0, 3-byte address, D8h)
3 2 1 0
31 30 29
MSb
SI
32 Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39
CS #
Figure 109 Sector Erase command sequence (ExtAdd = 1, D8h or 4-byte address, DCh)
The Bulk Erase (BE) command sets all bits to ‘1’ (all bytes are FFh) inside the entire flash memory array. Before the BE command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory array. If CS# is not driven HIGH after the last bit of instruction, the BE operation will not be executed.
As soon as CS# is driven into the logic HIGH state, the erase cycle will be initiated. With the erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a ‘1’ when the erase cycle is in progress and a ‘0’ when the erase cycle has been completed.
A BE command can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0’s. If the BP bits are not ‘0’, the BE command is not executed and E_ERR is not set. The BE command will skip any sectors protected by the DYB or PPB and the E_ERR status will not be set.
CS#
0 1 2 3 4 5 6 7
SCK
Instruction
SI
Figure 110 Bulk Erase command sequence
The Erase Suspend command, allows the system to interrupt a sector erase operation and then read from or program data to, any other sector. Erase Suspend is valid only during a sector erase operation. The Erase Suspend command is ignored if written during the Bulk Erase operation.
When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to suspend the erase operation and update the status bits. See Table 43.
Commands allowed after the Erase Suspend command is issued:
Read Status Register 1 (RDSR1 05h)
Read Status Register 2 (RDSR2 07h)
The Write in Progress (WIP) bit in Status Register 1 (SR1[0]) must be checked to know when the erase operation has stopped. The Erase Suspend bit in Status Register-2 (SR2[1]) can be used to determine if an erase operation has been suspended or was completed at the time WIP changes to ‘0’.
If the erase operation was completed during the suspend operation, a resume command is not needed and has no effect if issued. Erase Resume commands will be ignored unless an Erase operation is suspended.
See Table 52 for the commands allowed while erase is suspend.
After the erase operation has been suspended, the sector enters the erase-suspend mode. The system can read data from or program data to the device. Reading at any address within an erase-suspended sector produces undetermined data.
A WREN command is required before any command that will change non-volatile data, even during erase suspend.
The WRR and PPB Erase commands are not allowed during Erase Suspend, it is therefore not possible to alter the Block Protection or PPB bits during Erase Suspend. If there are sectors that may need programming during Erase suspend, these sectors should be protected only by DYB bits that can be turned off during Erase Suspend.
However, WRR is allowed immediately following the BRAC command; in this special case the WRR is interpreted as a write to the Bank Address Register, not a write to SR1 or CR1.
If a program command is sent for a location within an erase suspended sector the program operation will fail with the P_ERR bit set.
After an erase-suspended program operation is complete, the device returns to the erase-suspend mode. The system can determine the status of the program operation by reading the WIP bit in the Status Register, just as in the standard program operation.
The Erase Resume command 7Ah must be written to resume the erase operation if an Erase is suspend. Erase Resume commands will be ignored unless an Erase is Suspend.
After an Erase Resume command is sent, the WIP bit in the status register will be set to a ‘1’ and the erase operation will continue. Further Resume commands are ignored.
Erase operations may be interrupted as often as necessary e.g., an erase suspend command could immediately follow an erase resume command but, in order for an erase operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to tERS. See
tESL
Table 43.
tESL
CS#
SCK
Erase Suspend Instruction
Read Status
Erase Suspend Mode Command
SI 7 6 5 4 3 2 1 0 7 6 0 7 6 5
SO
7
0
Figure 111 Erase Suspend command sequence
Resume Sector or Block Erase
SO
7 6 5 4 3 2 1 0
MSb
High Impedance
SI
Instruction (7Ah)
SCK
0 1 2 3 4 5 6 7
CS#
Figure 112 Erase Resume command sequence
Table 52 Commands allowed during Program or Erase Suspend
Instruction name | Instruction code (Hex) | Allowed during Erase Suspend | Allowed during Program Suspend | Comment |
BRAC | B9 | X | X | Bank address register may need to be changed during a suspend to reach a sector for read or program. |
BRRD | 16 | X | X | Bank address register may need to be changed during a suspend to reach a sector for read or program. |
BRWR | 17 | X | X | Bank address register may need to be changed during a suspend to reach a sector for read or program. |
CLSR | 30 | X | – | Clear status may be used if a program operation fails during erase suspend. |
DYBRD | E0 | X | – | It may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. |
DYBWR | E1 | X | – | It may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. |
ERRS | 7A | X | – | Required to resume from erase suspend. |
Table 52 Commands allowed during Program or Erase Suspend (continued)
Instruction name | Instruction code (Hex) | Allowed during Erase Suspend | Allowed during Program Suspend | Comment |
DDRFR | 0D | X | X | All array reads allowed in suspend. |
4DDRFR | 0E | X | X | All array reads allowed in suspend. |
FAST_READ | 0B | X | X | All array reads allowed in suspend. |
4FAST_READ | 0C | X | X | All array reads allowed in suspend. |
MBR | FF | X | X | May need to reset a read operation during suspend. |
PGRS | 8A | X | X | Needed to resume a program operation. A program resume may also be used during nested program suspend within an erase suspend. |
PGSP | 85 | X | – | Program suspend allowed during erase suspend. |
PP | 02 | X | – | Required for array program during erase suspend. |
4PP | 12 | X | – | Required for array program during erase suspend. |
PPBRD | E2 | X | – | Allowed for checking persistent protection before attempting a program command during erase suspend. |
QPP | 32, 38 | X | – | Required for array program during erase suspend. |
4QPP | 34 | X | – | Required for array program during erase suspend. |
4READ | 13 | X | X | All array reads allowed in suspend. |
RDCR | 35 | X | X | |
DIOR | BB | X | X | All array reads allowed in suspend. |
4DIOR | BC | X | X | All array reads allowed in suspend. |
DOR | 3B | X | X | All array reads allowed in suspend. |
4DOR | 3C | X | X | All array reads allowed in suspend. |
DDRDIOR | BD | X | X | All array reads allowed in suspend. |
4DDRDIOR | BE | X | X | All array reads allowed in suspend. |
DDRQIOR | ED | X | X | All array reads allowed in suspend. |
DDRQIOR4 | EE | X | X | All array reads allowed in suspend. |
QIOR | EB | X | X | All array reads allowed in suspend. |
4QIOR | EC | X | X | All array reads allowed in suspend. |
QOR | 6B | X | X | All array reads allowed in suspend. |
4QOR | 6C | X | X | All array reads allowed in suspend. |
RDSR1 | 05 | X | X | Needed to read WIP to determine end of suspend process. |
RDSR2 | 07 | X | X | Needed to read suspend status to determine whether the operation is suspended or complete. |
READ | 03 | X | X | All array reads allowed in suspend. |
RESET | F0 | X | X | Reset allowed anytime. |
WREN | 06 | X | – | Required for program command within erase suspend. |
WRR | 01 | X | X | Bank register may need to be changed during a suspend to reach a sector needed for read or program. WRR is allowed when following BRAC. |
The OTP Program command programs data in the One Time Program region, which is in a different address space from the main array data. The OTP region is 1024 bytes so, the address bits from A23 to A10 must be ‘0’ for this command. See “OTP address space” on page 49 for details on the OTP region. The protocol of the OTP Program command is the same as the Page Program command. Before the OTP Program command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
To program the OTP array in bit granularity, the rest of the bits within a data byte can be set to ‘1’.
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSb MSb MSb
SI
Data Byte 512
Data Byte 3
Data Byte 2
SCK
40 41 42 43 44 45 46 47 48 49 59 51 52 53 54 55
CS#
7 6 5 4 3 2 1 0 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSb MSb
SI
Data Byte 1
24-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CS#
Each region in the OTP memory space can be programmed one or more times, provided that the region is not locked. Attempting to program zeros in a region that is locked will fail with the P_ERR bit in SR1 set to ‘1’ Programming ones, even in a protected area does not cause an error and does not set P_ERR. Subsequent OTP programming can be performed only on the un-programmed bits (that is, ‘1’ data).
4120
4121
4122
4123
4124
4125
4126
4127
Figure 113 OTP Program command sequence
The OTP Read command reads data from the OTP region. The OTP region is 1024 bytes so, the address bits from A23 to A10 must be ‘0’ for this command. See 2 for details on the OTP region. The protocol of the OTP Read command is similar to the Fast Read command except that it will not wrap to the starting address after the OTP address is at its maximum; instead, the data beyond the maximum OTP address will be undefined. Also, the OTP Read command is not affected by the latency code. The OTP read command always has one dummy byte of latency as shown below.
SO High Impedance 7
MSb
DATA OUT 2
DATA OUT 1
6 5 4 3 2
CS #
23 22 21
SI
Dummy Byte
24-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
1 0 7
MSb
3 2 1 0 7 6 5 4 3 2 1 0
Figure 114 OTP Read command sequence
The ASP Read instruction 2Bh is shifted into SI by the rising edge of the SCK signal. Then the 16-bit ASP register contents is shifted out on the serial output SO, least significant byte first. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read the ASP register continuously by providing multiples of 16 clock cycles. The maximum operating clock frequency for the ASP Read (ASPRD) command is 133 MHz.
Instruction
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
7
MSb
6 5 4 3 2
1 0
High Impedance
SO 7
MSb
Register Out Register Out
6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7
MSb MSb
Figure 115 ASPRD command
Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The ASPP command is entered by driving CS# to the logic LOW state, followed by the instruction and two data bytes on SI, least significant byte first. The ASP Register is two data bytes in length.
The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other programming operation.
CS# input must be driven to the logic HIGH state after the sixteenth bit of data has been latched in. If not, the ASPP command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed ASPP operation is initiated. While the ASPP operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a ‘1’ during the self-timed ASPP operation, and is a ‘0’ when it is completed. When the ASPP operation is completed, the Write Enable Latch (WEL) is set to a ‘0’.
5 4
7 6
MSb
1 0
7 6 5 4 3 2
MSb
High Impedance
SI
Register In
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS#
3 2 1 0 15 14 13 12 11 10 9 8
SO
Figure 116 ASPP command
The instruction E0h is latched into SI by the rising edge of the SCK signal. Followed by the 32-bit address selecting location ‘0’ within the desired sector (note, the high order address bits not used by a particular density device must be ‘0’). Then the 8-bit DYB access register contents are shifted out on the serial output SO. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read the same DYB access register continuously by providing multiples of eight clock cycles. The address of the DYB register does not increment so this is not a means to read the entire DYB array. Each location must be read with a separate DYB Read command. The maximum operating clock frequency for READ command is 133 MHz.
7 6 5 4 3 2 1 0 31 30 29
SI
32-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
CS#
DATA OUT 1
SO High Impedance 7 6 5 4 3 2 1 0
MSb
3 2 1 0
Figure 117 DYBRD command sequence
Before the DYB Write (DYBWR) command can be accepted by the device, a Write Enable (WREN) command must be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The DYBWR command is entered by driving CS# to the logic LOW state, followed by the instruction, the 32-bit address selecting location ‘0’ within the desired sector (note, the high order address bits not used by a particular density device must be ‘0’), then the data byte on SI. The DYB Access Register is one data byte in length.
The DYBWR command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other programming operation. CS# must be driven to the logic HIGH state after the eighth bit of data has been latched in. If not, the DYBWR command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed DYBWR operation is initiated. While the DYBWR operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a ‘1’ during the self-timed DYBWR operation, and is a ‘0’ when it is completed. When the DYBWR operation is completed, the Write Enable Latch (WEL) is set to a ‘0’.
3 2 1 0
1 0 7 6 5 4
MSb
7 6 5 4 3 2 1 0 31 30 29 3 2
MSb
SI
Data Byte 1
32-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
CS#
Figure 118 DYBWR command sequence
The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 32-bit address selecting location ‘0’ within the desired sector (note, the high order address bits not used by a particular density device must be ‘0’) Then the 8-bit PPB access register contents are shifted out on SO.
It is possible to read the same PPB access register continuously by providing multiples of eight clock cycles. The address of the PPB register does not increment so this is not a means to read the entire PPB array. Each location must be read with a separate PPB Read command. The maximum operating clock frequency for the PPB Read command is 133 MHz.
7 6 5 4 3 2 1 0 31 30 29
SI
32-Bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
CS#
DATA OUT 1
SO High Impedance 7 6 5 4 3 2 1 0
MSb
3 2 1 0
Figure 119 PPBRD command sequence
Before the PPB Program (PPBP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The PPBP command is entered by driving CS# to the logic LOW state, followed by the instruction, followed by the 32-bit address selecting location ‘0’ within the desired sector (note, the high order address bits not used by a particular density device must be ‘0’).
The PPBP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other programming operation.
CS# must be driven to the logic HIGH state after the last bit of address has been latched in. If not, the PPBP command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PPBP operation is initiated. While the PPBP operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a ‘1’ during the self-timed PPBP operation, and is a ‘0’ when it is completed. When the PPBP operation is completed, the Write Enable Latch (WEL) is set to a ‘0’.
SO
3 2 1 0
30 29
31
MSb
7 6 5 4 3 2 1 0
MSb
SI
32 bit Address
Instruction
SCK
0 1 2 3 4 5 6 7 8 9 10 35 36 37 38 39
CS #
High Impedance
Figure 120 PPBP command sequence
The PPB Erase (PPBE) command sets all PPB bits to ‘1’. Before the PPB Erase command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction E4h is shifted into SI by the rising edges of the SCK signal.
CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of the entire PPB memory array. Without CS# being driven to the logic HIGH state after the eighth bit of the instruction, the PPB erase operation will not be executed.
With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the operation has been completed. The WIP bit will indicate a ‘1’ when the erase cycle is in progress and a ‘0’ when the erase cycle has been completed. Erase suspend is not allowed during PPB Erase.
SO
7 6 5 4 3 2 1 0
MSb
High Impedance
SI
Instruction
SCK
0 1 2 3 4 5 6 7
CS#
Figure 121 PPB Erase command sequence
CS# SCK SI SO
Phase
The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is possible to read the PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock Register contents may only be read when the device is in standby state with no other operation in progress. It is recommended to check the Write-In Progress (WIP) bit of the Status Register before issuing a new command to the device.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Instruction | Register Read | Repeat Register Read |
Figure 122 PPB Lock Register Read command sequence
The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to ‘0’. Before the PLBWR command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The PLBWR command is entered by driving CS# to the logic LOW state, followed by the instruction.
CS# must be driven to the logic HIGH state after the eighth bit of instruction has been latched in. If not, the PLBWR command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PLBWR operation is initiated. While the PLBWR operation is in progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a ‘1’ during the self-timed PLBWR operation, and is a ‘0’ when it is completed. When the PLBWR operation is completed, the Write Enable Latch (WEL) is set to a ‘0’. The maximum clock frequency for the PLBWR command is 133 MHz.
SO
7 6 5 4 3 2 1 0
MSb
High Impedance
SI
Instruction
SCK
0 1 2 3 4 5 6 7
CS#
Figure 123 PPB Lock Bit Write command sequence
The correct password value may be read only after it is programmed and before the Password Mode has been selected by programming the Password Protection Mode bit to ‘0’ in the ASP Register (ASP[2]). After the Password Protection Mode is selected the PASSRD command is ignored.
The PASSRD command is shifted into SI. Then the 64-bit Password is shifted out on the serial output SO, least significant byte first, most significant bit of each byte first. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read the Password continuously by providing multiples of 64 clock cycles. The maximum operating clock frequency for the PASSRD command is 133 MHz.
7 6 5 4
SO
High Impedance
CS#
1 0
6 5 4 3 2
7
MSb
SI
Instruction
SCK
69 70 71 72
0 1 2 3 4 5 6 7 8 9 10 11
58 57 56 7
MSb MSb
Password Least Sig. Byte First
Figure 124 Password Read command sequence
Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded, the device sets the Write Enable Latch (WEL) to enable the PASSP operation.
The password can only be programmed before the Password Mode is selected by programming the Password Protection Mode bit to ‘0’ in the ASP Register (ASP[2]). After the Password Protection Mode is selected the PASSP command is ignored.
The PASSP command is entered by driving CS# to the logic LOW state, followed by the instruction and the password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length.
CS# must be driven to the logic HIGH state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSP command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PASSP operation is initiated. While the PASSP operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a ‘1’ during the self-timed PASSP cycle, and is a ‘0’ when it is completed. The PASSP command can report a program error in the P_ERR bit of the status register.
When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a ‘0’. The maximum clock frequency for the PASSP command is 133 MHz.
CS#
7 6 5 4 3 2 1 0
MSb
SI
Password
Instruction
SCK
68 69 70 71
0 1 2 3 4 5 6 7 8 9 10
6 5
59 58 57 56
SO
High Impedance
7
MSb
Figure 125 Password Program command sequence
The PASSU command is entered by driving CS# to the logic LOW state, followed by the instruction and the password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length.
CS# must be driven to the logic HIGH state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSU command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PASSU operation is initiated. While the PASSU operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a ‘1’ during the self-timed PASSU cycle, and is a ‘0’ when it is completed.
If the PASSU command supplied password does not match the hidden password in the Password Register, an error is reported by setting the P_ERR bit to ‘1’. The WIP bit of the status register also remains set to ‘1’. It is necessary to use the CLSR command to clear the status register, the RESET command to software reset the device, or drive the RESET# input LOW to initiate a hardware reset, in order to return the P_ERR and WIP bits to ‘0’. This returns the device to standby state, ready for new commands such as a retry of the PASSU command.
If the password does match, the PPB Lock bit is set to ‘1’. The maximum clock frequency for the PASSU command is 133 MHz.
0 1 2 3 4 5 6 7 8 9 10
CS#
7
MSb
7 6 5 4 3 2 1 0
SI
Password
Instruction
SCK
68 69 70 71
MSb
SO
High Impedance
6 5
59 58 57 56
Figure 126 Password Unlock command sequence
The Software Reset command (RESET) restores the device to its initial power up state, except for the volatile FREEZE bit in the Configuration register CR1[1] and the volatile PPB Lock bit in the PPB Lock Register. The Freeze bit and the PPB Lock bit will remain set at their last value prior to the software reset. To clear the FREEZE bit and set the PPB Lock bit to its protection mode selected power on state, a full power-on-reset sequence or hardware reset must be done. Note that the non-volatile bits in the configuration register, TBPROT, TBPARM, and BPNV, retain their previous state after a Software Reset. The Block Protection bits BP2, BP1, and BP0, in the status register will only be reset if they are configured as volatile via the BPNV bit in the Configuration Register (CR1[3]) and FREEZE is cleared to ‘0’. The software reset cannot be used to circumvent the FREEZE or PPB Lock bit protection mechanisms for the other security configuration bits. The reset command is executed when CS# is brought to HIGH state and requires tRPH time to execute.
CS#
0 1 2 3 4 5 6 7
SCK
Instruction
SI
Figure 127 Software Reset command sequence
The Mode Bit Reset (MBR) command can be used to return the device from continuous high performance read mode back to normal standby awaiting any new command. Because some device packages lack a hardware RESET# input and a device that is in a continuous high performance read mode may not recognize any normal SPI command, a system hardware reset or software reset command may not be recognized by the device. It is recommended to use the MBR command after a system reset when the RESET# signal is not available or, before sending a software reset, to ensure the device is released from continuous high performance read mode.
The MBR command sends Ones on SI or IO0 for 8 SCK cycles. IO1 to IO3 are “don’t care” during these cycles.
CSS #
0 1 2 3 4 5 6 7
SCK
Instruction (FFh)
SI
High Impedance
SO
Figure 128 Mode Bit Reset command sequence
Data integrity
Table 53 Erase endurance
Parameter | Minimum | Unit |
Program/Erase cycles per main flash array sectors | 100K | PE cycle |
Program/Erase cycles per PPB array or non-volatile register array[57] | 100K | PE cycle |
Note
Each write command to a non-volatile register causes a PE cycle on the entire non-volatile register array.
Table 54 Data retention
Parameter | Test conditions | Minimum time | Unit |
Data retention time | 10K Program/Erase Cycles | 20 | Years |
100K Program/Erase Cycles | 2 | Years |
Table 55 S25FL128S and S25FL256S instruction set (Sorted by instruction)
Instruction (Hex) | Command name | Command description | Maximum frequency (MHz) |
01 | WRR | Write Register (Status-1, Configuration-1) | 133 |
02 | PP | Page Program (3- or 4-byte address) | 133 |
03 | READ | Read (3- or 4-byte address) | 50 |
04 | WRDI | Write Disable | 133 |
05 | RDSR1 | Read Status Register-1 | 133 |
06 | WREN | Write Enable | 133 |
07 | RDSR2 | Read Status Register-2 | 133 |
0B | FAST_READ | Fast Read (3- or 4-byte address) | 133 |
0C | 4FAST_READ | Fast Read (4-byte address) | 133 |
0D | DDRFR | DDR Fast Read (3- or 4-byte address) | 80 |
0E | 4DDRFR | DDR Fast Read (4-byte address) | 80 |
12 | 4PP | Page Program (4-byte address) | 133 |
13 | 4READ | Read (4-byte address) | 50 |
14 | ABRD | AutoBoot Register Read | 133 |
15 | ABWR | AutoBoot Register Write | 133 |
16 | BRRD | Bank Register Read | 133 |
17 | BRWR | Bank Register Write | 133 |
18 | ECCRD | ECC Read | 133 |
20 | P4E | Parameter 4 KB-sector Erase (3- or 4-byte address) | 133 |
21 | 4P4E | Parameter 4 KB-sector Erase (4-byte address) | 133 |
2B | ASPRD | ASP Read | 133 |
2F | ASPP | ASP Program | 133 |
30 | CLSR | Clear Status Register - Erase/Program Fail Reset | 133 |
32 | QPP | Quad Page Program (3- or 4-byte address) | 80 |
34 | 4QPP | Quad Page Program (4-byte address) | 80 |
35 | RDCR | Read Configuration Register-1 | 133 |
38 | QPP | Quad Page Program (3- or 4-byte address) | 80 |
3B | DOR | Read Dual Out (3- or 4-byte address) | 104 |
3C | 4DOR | Read Dual Out (4-byte address) | 104 |
41 | DLPRD | Data Learning Pattern Read | 133 |
42 | OTPP | OTP Program | 133 |
43 | PNVDLR | Program NV Data Learning Register | 133 |
4A | WVDLR | Write Volatile Data Learning Register | 133 |
4B | OTPR | OTP Read | 133 |
60 | BE | Bulk Erase | 133 |
6B | QOR | Read Quad Out (3- or 4-byte address) | 104 |
Table 55 S25FL128S and S25FL256S instruction set (Sorted by instruction) (continued)
Instruction (Hex) | Command name | Command description | Maximum frequency (MHz) |
6C | 4QOR | Read Quad Out (4-byte address) | 104 |
75 | ERSP | Erase Suspend | 133 |
7A | ERRS | Erase Resume | 133 |
85 | PGSP | Program Suspend | 133 |
8A | PGRS | Program Resume | 133 |
90 | READ_ID (REMS) | Read Electronic Manufacturer Signature | 133 |
9F | RDID | Read ID (JEDEC Manufacturer ID and JEDEC CFI) | 133 |
A3 | MPM | Reserved for Multi-I/O-High Perf Mode (MPM) | 133 |
A6 | PLBWR | PPB Lock Bit Write | 133 |
A7 | PLBRD | PPB Lock Bit Read | 133 |
AB | RES | Read Electronic Signature | 50 |
B9 | BRAC | Bank Register Access (Legacy Command formerly used for Deep Power Down) | 133 |
BB | DIOR | Dual I/O Read (3- or 4-byte address) | 104 |
BC | 4DIOR | Dual I/O Read (4-byte address) | 104 |
BD | DDRDIOR | DDR Dual I/O Read (3- or 4-byte address) | 80 |
BE | 4DDRDIOR | DDR Dual I/O Read (4-byte address) | 80 |
C7 | BE | Bulk Erase (alternate command) | 133 |
D8 | SE | Erase 64 KB or 256 KB (3- or 4-byte address) | 133 |
DC | 4SE | Erase 64 KB or 256 KB (4-byte address) | 133 |
E0 | DYBRD | DYB Read | 133 |
E1 | DYBWR | DYB Write | 133 |
E2 | PPBRD | PPB Read | 133 |
E3 | PPBP | PPB Program | 133 |
E4 | PPBE | PPB Erase | 133 |
E5 | Reserved-E5 | Reserved | – |
E6 | Reserved-E6 | Reserved | – |
E7 | PASSRD | Password Read | 133 |
E8 | PASSP | Password Program | 133 |
E9 | PASSU | Password Unlock | 133 |
EB | QIOR | Quad I/O Read (3- or 4-byte address) | 104 |
EC | 4QIOR | Quad I/O Read (4-byte address) | 104 |
ED | DDRQIOR | DDR Quad I/O Read (3- or 4-byte address) | 80 |
EE | 4DDRQIOR | DDR Quad I/O Read (4-byte address) | 80 |
F0 | RESET | Software Reset | 133 |
FF | MBR | Mode Bit Reset | 133 |
Table 56 Manufacturer and device ID
Byte address | Data | Description |
00h | 01h | Manufacturer ID for Infineon |
01h | 20h (128 Mb) 02h (256 Mb) | Device ID Most Significant Byte - Memory Interface Type |
02h | 18h (128 Mb) 19h (256 Mb) | Device ID Least Significant Byte - Density |
03h | 4Dh | ID-CFI Length - number bytes following. Adding this value to the current location of 03h gives the address of the last valid location in the ID-CFI address map. A value of 00h indicates the entire 512-byte ID-CFI space must be read because the actual length of the ID-CFI information is longer than can be indicated by this legacy single byte field. The value is OPN dependent. |
04h | 00h (Uniform 256-KB sectors) 01h (4-KB parameter sectors with uniform 64-KB sectors) | Sector Architecture |
05h | 80h (FL-S Family) | Family ID |
06h | xxh | ASCII characters for Model See “Ordering information” on page 154 for the model number definitions. |
07h | xxh | |
08h | xxh | Reserved |
09h | xxh | Reserved |
0Ah | xxh | Reserved |
0Bh | xxh | Reserved |
0Ch | xxh | Reserved |
0Dh | xxh | Reserved |
0Eh | xxh | Reserved |
0Fh | xxh | Reserved |
Table 57 CFI query identification string
Byte address | Data | Description |
10h 11h 12h | 51h 52h 59h | Query Unique ASCII string “QRY” |
13h 14h | 02h 00h | Primary OEM Command Set FL-P backward compatible command set ID |
15h 16h | 40h 00h | Address for Primary Extended Table |
17h 18h | 53h 46h | Alternate OEM Command Set ASCII characters “FS” for SPI (F) interface, S Technology |
19h 1Ah | 51h 00h | Address for Alternate OEM Extended Table |
Table 58 CFI system interface string
Byte address | Data | Description |
1Bh | 27h | VCC Min. (erase/program): 100 millivolts |
1Ch | 36h | VCC Max. (erase/program): 100 millivolts |
1Dh | 00h | VPP Min. voltage (00h = no VPP present) |
1Eh | 00h | VPP Max. voltage (00h = no VPP present) |
1Fh | 06h | Typical timeout per single byte program 2N µs |
20h | 08h (256B page) 09h (512B page) | Typical timeout for Min. size Page program 2N µs (00h = not supported) |
21h | 08h (4 KB or 64 KB) 09h (256 KB) | Typical timeout per individual sector erase 2N ms |
22h | 0Fh (128 Mb) 10h (256 Mb) | Typical timeout for full chip erase 2N ms (00h = not supported) |
23h | 02h | Max. timeout for byte program 2N times typical |
24h | 02h | Max. timeout for page program 2N times typical |
25h | 03h | Max. timeout per individual sector erase 2N times typical |
26h | 03h | Max. timeout for full chip erase 2N times typical (00h = not supported) |
Table 59 Device geometry definition for 128-Mb and 256-Mb bottom boot initial delivery state[58]
Byte address | Data | Description |
27h | 18h (128 Mb) 19h (256 Mb) | Device size = 2N bytes |
28h | 02h | Flash device interface description: 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 0004h = Single I/O SPI, 3-byte address 0005h = Multi I/O SPI, 3-byte address 0102h = Multi I/O SPI, 3- or 4-byte address |
29h | 01h | |
2Ah | 08h | Max. number of bytes in multi-byte write = 2N (0000 = Not supported 0008h = 256B page 0009h = 512B page) |
2Bh | 00h | |
2Ch | 02h | Number of Erase Block Regions within device 1 = Uniform device, 2 = Boot device |
Note
FL-S 128 Mb and 256-Mb devices have either a hybrid sector architecture with thirty two 4-KB sectors and all remaining sectors of 64-KB or with uniform 256-KB sectors. Devices with the hybrid sector architecture are initially shipped from Infineon with the 4 KB sectors located at the bottom of the array address map. However, the device configuration TBPARM bit CR1[2] may be programed to invert the sector map to place the 4-KB sectors at the top of the array address map. The CFI geometry information of the above table is relevant only to the initial delivery state of a hybrid sector device. The flash device driver software must examine the TBPARM bit to determine if the sector map was inverted at a later time.
Table 59 Device geometry definition for 128-Mb and 256-Mb bottom boot initial delivery state[58] (con- tinued)
Byte address | Data | Description |
2Dh | 1Fh | Erase Block Region 1 Information (refer to JEDEC JEP137): 32 sectors = 32-1 = 001Fh 4-KB sectors = 256 bytes x 0010h |
2Eh | 00h | |
2Fh | 10h | |
30h | 00h | |
31h | FDh | Erase Block Region 2 Information: 254 sectors = 254-1 = 00FDh (128 Mb) 510 sectors = 510-1 = 01FDh (256 Mb) 64-KB sectors = 0100h x 256 bytes |
32h | 00h (128 Mb) 01h (256 Mb) | |
33h | 00h | |
34h | 01h | |
35h thru 3Fh | FFh | RFU |
Note
FL-S 128 Mb and 256-Mb devices have either a hybrid sector architecture with thirty two 4-KB sectors and all remaining sectors of 64-KB or with uniform 256-KB sectors. Devices with the hybrid sector architecture are initially shipped from Infineon with the 4 KB sectors located at the bottom of the array address map. However, the device configuration TBPARM bit CR1[2] may be programed to invert the sector map to place the 4-KB sectors at the top of the array address map. The CFI geometry information of the above table is relevant only to the initial delivery state of a hybrid sector device. The flash device driver software must examine the TBPARM bit to determine if the sector map was inverted at a later time.
Table 60 Device geometry definition for 128-Mb and 256-Mb uniform sector devices
Byte address | Data | Description |
27h | 18h (128 Mb) 19h (256 Mb) | Device size = 2N bytes |
28h | 02h | Flash device interface description: 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 0004h = Single I/O SPI, 3-byte address 0005h = Multi I/O SPI, 3-byte address 0102h = Multi I/O SPI, 3- or 4-byte address |
29h | 01h | |
2Ah | 09h | Max. number of bytes in multi-byte write = 2N (0000 = not supported 0008h = 256B page 0009h = 512B page) |
2Bh | 00h | |
2Ch | 01h | Number of Erase Block Regions within device 1 = Uniform device, 2 = Boot device |
2Dh | 3Fh (128 Mb) 7Fh (256 Mb) | Erase Block Region 1 Information (refer to JEDEC JEP137): 64 sectors = 64-1 = 003Fh (128 Mb) 128 sectors = 128-1 = 007Fh (256 Mb) 256-KB sectors = 256 bytes x 0400h |
2Eh | 00h | |
2Fh | 00h | |
30h | 04h | |
31h thru 3Fh | FFh | RFU |
Table 61 CFI primary vendor-specific extended query
Byte address | Data | Description |
40h | 50h | Query-unique ASCII string “PRI” |
41h | 52h | |
42h | 49h | |
43h | 31h | Major version number = 1, ASCII |
44h | 33h | Minor version number = 3, ASCII |
45h | 21h | Address Sensitive Unlock (Bits 1-0) 00b = Required 01b = Not Required Process technology (Bits 5-2) 0000b = 0.23 µm Floating Gate 0001b = 0.17 µm Floating Gate 0010b = 0.23 µm MIRRORBIT™ 0011b = 0.11 µm Floating Gate 0100b = 0.11 µm MIRRORBIT™ 0101b = 0.09 µm MIRRORBIT™ 1000b = 0.065 µm MIRRORBIT™ |
46h | 02h | Erase Suspend 0 = Not Supported 1 = Read Only 2 = Read and Program |
47h | 01h | Sector Protect 00 = Not Supported X = Number of sectors in group |
48h | 00h | Temporary Sector Unprotect 00 = Not Supported 01 = Supported |
49h | 08h | Sector Protect/Unprotect Scheme 04 = High Voltage Method 05 = Software Command Locking Method 08 = Advanced Sector Protection Method 09 = Secure |
4Ah | 00h | Simultaneous Operation 00 = Not Supported X = Number of Sectors |
4Bh | 01h | Burst Mode (Synchronous sequential read) support 00 = Not Supported 01 = Supported |
4Ch | xxh | Page Mode Type, model dependent 00 = Not Supported 01 = 4 Word Read Page 02 = 8 Read Word Page 03 = 256-Byte Program Page 04 = 512-Byte Program Page |
4Dh | 00h | ACC (Acceleration) Supply Minimum 00 = Not Supported, 100 mV |
Table 61 CFI primary vendor-specific extended query (continued)
Byte address | Data | Description |
4Eh | 00h | ACC (Acceleration) Supply Maximum 00 = Not Supported, 100 mV |
4Fh | 07h | WP# Protection 01 = Whole Chip 04 = Uniform Device with Bottom WP Protect 05 = Uniform Device with Top WP Protect 07 = Uniform Device with Top or Bottom Write Protect (user select) |
50h | 01h | Program Suspend 00 = Not Supported 01 = Supported |
The Alternate Vendor-Specific Extended Query provides information related to the expanded command set provided by the FL-S family. The alternate query parameters use a format in which each parameter begins with an identifier byte and a parameter length byte. Driver software can check each parameter ID and can use the length value to skip to the next parameter if the parameter is not needed or not recognized by the software.
Table 62 CFI alternate vendor-specific extended query header
Byte address | Data | Description |
51h | 41h | Query-unique ASCII string “ALT” |
52h | 4Ch | |
53h | 54h | |
54h | 32h | Major version number = 2, ASCII |
55h | 30h | Minor version number = 0, ASCII |
Table 63 CFI alternate vendor-specific extended query parameter 0
Parameter relative byte address offset | Data | Description |
00h | 00h | Parameter ID (Ordering Part Number) |
01h | 10h | Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) |
02h | 53h | ASCII “S” for manufacturer (Infineon) |
03h | 32h | ASCII “25” for Product Characters (Single Die SPI) |
04h | 35h | |
05h | 46h | ASCII “FL” for Interface Characters (SPI 3 Volt) |
06h | 4Ch | |
07h | 31h (128 Mb) 32h (256 Mb) | ASCII characters for density |
08h | 32h (128 Mb) 35h (256 Mb) | |
09h | 38h (128 Mb) 36h (256 Mb) | |
0Ah | 53h | ASCII “S” for technology (65-nm MIRRORBIT™) |
0Bh | xxh | Reserved for Future Use (RFU) |
0Ch | ||
0Dh | ||
0Eh | ||
0Fh | ||
10h | ||
11h |
Table 64 CFI alternate vendor-specific extended query parameter 80h address options
Parameter relative byte address offset | Data | Description |
00h | 80h | Parameter ID (address options) |
01h | 01h | Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) |
02h | F0h | Bits 7:4 - Reserved = 1111b Bit 3 - AutoBoot support - Ye s= 0b, No = 1b Bit 2 - 4-byte address instructions supported - Yes = 0b, No = 1b Bit 1 - Bank address + 3-byte address instructions supported - Yes = 0b, No = 1b Bit 0 - 3-byte address instructions supported - Yes = 0b, No = 1b |
Table 65 CFI alternate vendor-specific extended query parameter 84h suspend commands
Parameter relative byte address offset | Data | Description |
00h | 84h | Parameter ID (Suspend Commands |
01h | 08h | Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) |
02h | 85h | Program suspend instruction code |
03h | 2Dh | Program suspend latency maximum (µs) |
04h | 8Ah | Program resume instruction code |
05h | 64h | Program resume to next suspend typical (µs) |
06h | 75h | Erase suspend instruction code |
07h | 2Dh | Erase suspend latency maximum (µs) |
08h | 7Ah | Erase resume instruction code |
09h | 64h | Erase resume to next suspend typical (µs) |
Table 66 CFI alternate vendor-specific extended query parameter 88h data protection
Parameter relative byte address offset | Data | Description |
00h | 88h | Parameter ID (Data Protection) |
01h | 04h | Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) |
02h | 0Ah | OTP size 2N bytes, FFh = not supported |
03h | 01h | OTP address map format, 01h = FL-S format, FFh = not supported |
04h | xxh | Block Protect Type, model dependent 00h = FL-P, FL-S, FFh = not supported |
05h | xxh | Advanced Sector Protection type, model dependent 01h = FL-S ASP |
Table 67 CFI alternate vendor-specific extended query parameter 8Ch reset timing
Parameter relative byte address offset | Data | Description |
00h | 8Ch | Parameter ID (Reset Timing) |
01h | 06h | Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) |
02h | 96h | POR maximum value |
03h | 01h | POR maximum exponent 2N µs |
04h | FFh (without separate RESET#) 23h (with separate RESET #) | Hardware Reset maximum value |
05h | 00h | Hardware Reset maximum exponent 2N µs |
06h | 23h | Software Reset maximum value, FFh = not supported |
07h | 00h | Software Reset maximum exponent 2N µs |
Table 68 CFI alternate vendor-specific extended query parameter 90h - HPLC(SDR)
Parameter relative byte address offset | Data | Description |
00h | 90h | Parameter ID (Latency Code Table) |
01h | 56h | Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) |
02h | 06h | Number of rows |
03h | 0Eh | Row length in bytes |
04h | 46h | Start of header (row 1), ASCII “F” for frequency column header |
05h | 43h | ASCII “C” for Code column header |
06h | 03h | Read 3-byte address instruction |
07h | 13h | Read 4-byte address instruction |
08h | 0Bh | Read Fast 3-byte address instruction |
09h | 0Ch | Read Fast 4-byte address instruction |
0Ah | 3Bh | Read Dual Out 3-byte address instruction |
0Bh | 3Ch | Read Dual Out 4-byte address instruction |
0Ch | 6Bh | Read Quad Out 3-byte address instruction |
0Dh | 6Ch | Read Quad Out 4-byte address instruction |
0Eh | BBh | Dual I/O Read 3-byte address instruction |
0Fh | BCh | Dual I/O Read 4-byte address instruction |
10h | EBh | Quad I/O Read 3-byte address instruction |
11h | ECh | Quad I/O Read 4-byte address instruction |
12h | 32h | Start of row 2, SCK frequency limit for this row (50 MHz) |
13h | 03h | Latency Code for this row (11b) |
14h | 00h | Read mode cycles |
15h | 00h | Read latency cycles |
16h | 00h | Read Fast mode cycles |
17h | 00h | Read Fast latency cycles |
18h | 00h | Read Dual Out mode cycles |
19h | 00h | Read Dual Out latency cycles |
1Ah | 00h | Read Quad Out mode cycles |
1Bh | 00h | Read Quad Out latency cycles |
1Ch | 00h | Dual I/O Read mode cycles |
1Dh | 04h | Dual I/O Read latency cycles |
1Eh | 02h | Quad I/O Read mode cycles |
1Fh | 01h | Quad I/O Read latency cycles |
20h | 50h | Start of row 3, SCK frequency limit for this row (80 MHz) |
21h | 00h | Latency Code for this row (00b) |
22h | FFh | Read mode cycles (FFh = command not supported at this frequency) |
23h | FFh | Read latency cycles |
Table 68 CFI alternate vendor-specific extended query parameter 90h - HPLC(SDR) (continued)
Parameter relative byte address offset | Data | Description |
24h | 00h | Read Fast mode cycles |
25h | 08h | Read Fast latency cycles |
26h | 00h | Read Dual Out mode cycles |
27h | 08h | Read Dual Out latency cycles |
28h | 00h | Read Quad Out mode cycles |
29h | 08h | Read Quad Out latency cycles |
2Ah | 00h | Dual I/O Read mode cycles |
2Bh | 04h | Dual I/O Read latency cycles |
2Ch | 02h | Quad I/O Read mode cycles |
2Dh | 04h | Quad I/O Read latency cycles |
2Eh | 5Ah | Start of row 4, SCK frequency limit for this row (90 MHz) |
2Fh | 01h | Latency Code for this row (01b) |
30h | FFh | Read mode cycles (FFh = command not supported at this frequency) |
31h | FFh | Read latency cycles |
32h | 00h | Read Fast mode cycles |
33h | 08h | Read Fast latency cycles |
34h | 00h | Read Dual Out mode cycles |
35h | 08h | Read Dual Out latency cycles |
36h | 00h | Read Quad Out mode cycles |
37h | 08h | Read Quad Out latency cycles |
38h | 00h | Dual I/O Read mode cycles |
39h | 05h | Dual I/O Read latency cycles |
3Ah | 02h | Quad I/O Read mode cycles |
3Bh | 04h | Quad I/O Read latency cycles |
3Ch | 68h | Start of row 5, SCK frequency limit for this row (104 MHz) |
3Dh | 02h | Latency Code for this row (10b) |
3Eh | FFh | Read mode cycles (FFh = command not supported at this frequency) |
3Fh | FFh | Read latency cycles |
40h | 00h | Read Fast mode cycles |
41h | 08h | Read Fast latency cycles |
42h | 00h | Read Dual Out mode cycles |
43h | 08h | Read Dual Out latency cycles |
44h | 00h | Read Quad Out mode cycles |
45h | 08h | Read Quad Out latency cycles |
46h | 00h | Dual I/O Read mode cycles |
47h | 06h | Dual I/O Read latency cycles |
48h | 02h | Quad I/O Read mode cycles |
Table 68 CFI alternate vendor-specific extended query parameter 90h - HPLC(SDR) (continued)
Parameter relative byte address offset | Data | Description |
49h | 05h | Quad I/O Read latency cycles |
4Ah | 85h | Start of row 6, SCK frequency limit for this row (133 MHz) |
4Bh | 02h | Latency Code for this row (10b) |
4Ch | FFh | Read mode cycles (FFh = command not supported at this frequency) |
4Dh | FFh | Read latency cycles |
4Eh | 00h | Read Fast mode cycles |
4Fh | 08h | Read Fast latency cycles |
50h | FFh | Read Dual Out mode cycles |
51h | FFh | Read Dual Out latency cycles |
52h | FFh | Read Quad Out mode cycles |
53h | FFh | Read Quad Out latency cycles |
54h | FFh | Dual I/O Read mode cycles |
55h | FFh | Dual I/O Read latency cycles |
56h | FFh | Quad I/O Read mode cycles |
57h | FFh | Quad I/O Read latency cycles |
Table 69 CFI alternate vendor-specific extended query parameter 9Ah - HPLC DDR
Parameter relative byte address offset | Data | Description |
00h | 9Ah | Parameter ID (Latency Code Table) |
01h | 2Ah | Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) |
02h | 05h | Number of rows |
03h | 08h | Row length in bytes |
04h | 46h | Start of header (row 1), ASCII “F” for frequency column header |
05h | 43h | ASCII “C” for Code column header |
06h | 0Dh | Read Fast DDR 3-byte address instruction |
07h | 0Eh | Read Fast DDR 4-byte address instruction |
08h | BDh | DDR Dual I/O Read 3-byte address instruction |
09h | BEh | DDR Dual I/O Read 4-byte address instruction |
0Ah | EDh | Read DDR Quad I/O 3-byte address instruction |
0Bh | EEh | Read DDR Quad I/O 4-byte address instruction |
0Ch | 32h | Start of row 2, SCK frequency limit for this row (50 MHz) |
0Dh | 03h | Latency Code for this row (11b) |
0Eh | 00h | Read Fast DDR mode cycles |
0Fh | 04h | Read Fast DDR latency cycles |
10h | 00h | DDR Dual I/O Read mode cycles |
11h | 04h | DDR Dual I/O Read latency cycles |
Table 69 CFI alternate vendor-specific extended query parameter 9Ah - HPLC DDR (continued)
Parameter relative byte address offset | Data | Description |
12h | 01h | Read DDR Quad I/O mode cycles |
13h | 03h | Read DDR Quad I/O latency cycles |
14h | 42h | Start of row 3, SCK frequency limit for this row (66 MHz) |
15h | 00h | Latency Code for this row (00b) |
16h | 00h | Read Fast DDR mode cycles |
17h | 05h | Read Fast DDR latency cycles |
18h | 00h | DDR Dual I/O Read mode cycles |
19h | 06h | DDR Dual I/O Read latency cycles |
1Ah | 01h | Read DDR Quad I/O mode cycles |
1Bh | 06h | Read DDR Quad I/O latency cycles |
1Ch | 42h | Start of row 4, SCK frequency limit for this row (66 MHz) |
1Dh | 01h | Latency Code for this row (01b) |
1Eh | 00h | Read Fast DDR mode cycles |
1Fh | 06h | Read Fast DDR latency cycles |
20h | 00h | DDR Dual I/O Read mode cycles |
21h | 07h | DDR Dual I/O Read latency cycles |
22h | 01h | Read DDR Quad I/O mode cycles |
23h | 07h | Read DDR Quad I/O latency cycles |
24h | 42h | Start of row 5, SCK frequency limit for this row (66 MHz) |
25h | 02h | Latency Code for this row (10b) |
26h | 00h | Read Fast DDR mode cycles |
27h | 07h | Read Fast DDR latency cycles |
28h | 00h | DDR Dual I/O Read mode cycles |
29h | 08h | DDR Dual I/O Read latency cycles |
2Ah | 01h | Read DDR Quad I/O mode cycles |
2Bh | 08h | Read DDR Quad I/O latency cycles |
Table 70 CFI alternate vendor-specific extended query parameter 90h - EHPLC (SDR)
Parameter relative byte address offset | Data | Description |
00h | 90h | Parameter ID (Latency Code Table) |
01h | 56h | Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) |
02h | 06h | Number of rows |
03h | 0Eh | Row length in bytes |
04h | 46h | Start of header (row 1), ASCII “F” for frequency column header |
05h | 43h | ASCII “C” for Code column header |
06h | 03h | Read 3-byte address instruction |
07h | 13h | Read 4-byte address instruction |
Table 70 CFI alternate vendor-specific extended query parameter 90h - EHPLC (SDR) (continued)
Parameter relative byte address offset | Data | Description |
08h | 0Bh | Read Fast 3-byte address instruction |
09h | 0Ch | Read Fast 4-byte address instruction |
0Ah | 3Bh | Read Dual Out 3-byte address instruction |
0Bh | 3Ch | Read Dual Out 4-byte address instruction |
0Ch | 6Bh | Read Quad Out 3-byte address instruction |
0Dh | 6Ch | Read Quad Out 4-byte address instruction |
0Eh | BBh | Dual I/O Read 3-byte address instruction |
0Fh | BCh | Dual I/O Read 4-byte address instruction |
10h | EBh | Quad I/O Read 3-byte address instruction |
11h | ECh | Quad I/O Read 4-byte address instruction |
12h | 32h | Start of row 2, SCK frequency limit for this row (50 MHz) |
13h | 03h | Latency Code for this row (11b) |
14h | 00h | Read mode cycles |
15h | 00h | Read latency cycles |
16h | 00h | Read Fast mode cycles |
17h | 00h | Read Fast latency cycles |
18h | 00h | Read Dual Out mode cycles |
19h | 00h | Read Dual Out latency cycles |
1Ah | 00h | Read Quad Out mode cycles |
1Bh | 00h | Read Quad Out latency cycles |
1Ch | 04h | Dual I/O Read mode cycles |
1Dh | 00h | Dual I/O Read latency cycles |
1Eh | 02h | Quad I/O Read mode cycles |
1Fh | 01h | Quad I/O Read latency cycles |
20h | 50h | Start of row 3, SCK frequency limit for this row (80 MHz) |
21h | 00h | Latency Code for this row (00b) |
22h | FFh | Read mode cycles (FFh = command not supported at this frequency) |
23h | FFh | Read latency cycles |
24h | 00h | Read Fast mode cycles |
25h | 08h | Read Fast latency cycles |
26h | 00h | Read Dual Out mode cycles |
27h | 08h | Read Dual Out latency cycles |
28h | 00h | Read Quad Out mode cycles |
29h | 08h | Read Quad Out latency cycles |
2Ah | 04h | Dual I/O Read mode cycles |
2Bh | 00h | Dual I/O Read latency cycles |
2Ch | 02h | Quad I/O Read mode cycles |
2Dh | 04h | Quad I/O Read latency cycles |
Table 70 CFI alternate vendor-specific extended query parameter 90h - EHPLC (SDR) (continued)
Parameter relative byte address offset | Data | Description |
2Eh | 5Ah | Start of row 4, SCK frequency limit for this row (90 MHz) |
2Fh | 01h | Latency Code for this row (01b) |
30h | FFh | Read mode cycles (FFh = command not supported at this frequency) |
31h | FFh | Read latency cycles |
32h | 00h | Read Fast mode cycles |
33h | 08h | Read Fast latency cycles |
34h | 00h | Read Dual Out mode cycles |
35h | 08h | Read Dual Out latency cycles |
36h | 00h | Read Quad Out mode cycles |
37h | 08h | Read Quad Out latency cycles |
38h | 04h | Dual I/O Read mode cycles |
39h | 01h | Dual I/O Read latency cycles |
3Ah | 02h | Quad I/O Read mode cycles |
3Bh | 04h | Quad I/O Read latency cycles |
3Ch | 68h | Start of row 5, SCK frequency limit for this row (104 MHz) |
3Dh | 02h | Latency Code for this row (10b) |
3Eh | FFh | Read mode cycles (FFh = command not supported at this frequency) |
3Fh | FFh | Read latency cycles |
40h | 00h | Read Fast mode cycles |
41h | 08h | Read Fast latency cycles |
42h | 00h | Read Dual Out mode cycles |
43h | 08h | Read Dual Out latency cycles |
44h | 00h | Read Quad Out mode cycles |
45h | 08h | Read Quad Out latency cycles |
46h | 04h | Dual I/O Read mode cycles |
47h | 02h | Dual I/O Read latency cycles |
48h | 02h | Quad I/O Read mode cycles |
49h | 05h | Quad I/O Read latency cycles |
4Ah | 85h | Start of row 6, SCK frequency limit for this row (133 MHz) |
4Bh | 02h | Latency Code for this row (10b) |
4Ch | FFh | Read mode cycles (FFh = command not supported at this frequency) |
4Dh | FFh | Read latency cycles |
4Eh | 00h | Read Fast mode cycles |
4Fh | 08h | Read Fast latency cycles |
50h | FFh | Read Dual Out mode cycles |
51h | FFh | Read Dual Out latency cycles |
52h | FFh | Read Quad Out mode cycles |
Table 70 CFI alternate vendor-specific extended query parameter 90h - EHPLC (SDR) (continued)
Parameter relative byte address offset | Data | Description |
53h | FFh | Read Quad Out latency cycles |
54h | FFh | Dual I/O Read mode cycles |
55h | FFh | Dual I/O Read latency cycles |
56h | FFh | Quad I/O Read mode cycles |
57h | FFh | Quad I/O Read latency cycles |
Table 71 CFI alternate vendor-specific extended query parameter 9Ah - EHPLC DDR
Parameter relative byte address offset | Data | Description |
00h | 9Ah | Parameter ID (Latency Code Table) |
01h | 2Ah | Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) |
02h | 05h | Number of rows |
03h | 08h | Row length in bytes |
04h | 46h | Start of header (row 1), ASCII “F” for frequency column header |
05h | 43h | ASCII “C” for Code column header |
06h | 0Dh | Read Fast DDR 3-byte address instruction |
07h | 0Eh | Read Fast DDR 4-byte address instruction |
08h | BDh | DDR Dual I/O Read 3-byte address instruction |
09h | BEh | DDR Dual I/O Read 4-byte address instruction |
0Ah | EDh | Read DDR Quad I/O 3-byte address instruction |
0Bh | EEh | Read DDR Quad I/O 4-byte address instruction |
0Ch | 32h | Start of row 2, SCK frequency limit for this row (50 MHz) |
0Dh | 03h | Latency Code for this row (11b) |
0Eh | 04h | Read Fast DDR mode cycles |
0Fh | 01h | Read Fast DDR latency cycles |
10h | 02h | DDR Dual I/O Read mode cycles |
11h | 02h | DDR Dual I/O Read latency cycles |
12h | 01h | Read DDR Quad I/O mode cycles |
13h | 03h | Read DDR Quad I/O latency cycles |
14h | 42h | Start of row 3, SCK frequency limit for this row (66 MHz) |
15h | 00h | Latency Code for this row (00b) |
16h | 04h | Read Fast DDR mode cycles |
17h | 02h | Read Fast DDR latency cycles |
18h | 02h | DDR Dual I/O Read mode cycles |
19h | 04h | DDR Dual I/O Read latency cycles |
1Ah | 01h | Read DDR Quad I/O mode cycles |
1Bh | 06h | Read DDR Quad I/O latency cycles |
1Ch | 42h | Start of row 4, SCK frequency limit for this row (66 MHz) |
Table 71 CFI alternate vendor-specific extended query parameter 9Ah - EHPLC DDR (continued)
Parameter relative byte address offset | Data | Description |
1Dh | 01h | Latency Code for this row (01b) |
1Eh | 04h | Read Fast DDR mode cycles |
1Fh | 04h | Read Fast DDR latency cycles |
20h | 02h | DDR Dual I/O Read mode cycles |
21h | 05h | DDR Dual I/O Read latency cycles |
22h | 01h | Read DDR Quad I/O mode cycles |
23h | 07h | Read DDR Quad I/O latency cycles |
24h | 42h | Start of row 5, SCK frequency limit for this row (66 MHz) |
25h | 02h | Latency Code for this row (10b) |
26h | 04h | Read Fast DDR mode cycles |
27h | 05h | Read Fast DDR latency cycles |
28h | 02h | DDR Dual I/O Read mode cycles |
29h | 06h | DDR Dual I/O Read latency cycles |
2Ah | 01h | Read DDR Quad I/O mode cycles |
2Bh | 08h | Read DDR Quad I/O latency cycles |
Table 72 CFI alternate vendor-specific extended query parameter F0h RFU
Parameter relative byte address offset | Data | Description |
00h | F0h | Parameter ID (RFU) |
01h | 0Fh | Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) |
02h | FFh | RFU |
... | FFh | RFU |
10h | FFh | RFU |
This parameter type (Parameter ID F0h) may appear multiple times and have a different length each time. The parameter is used to reserve space in the ID-CFI map or to force space (pad) to align a following parameter to a required boundary.
The CFI Primary Vendor-Specific Extended Query is extended to include Electronic Marking information for device traceability.
Address | Data field | # of bytes | Data format | Example of actual data | Hex read out of example data |
(SA) + 0180h | Size of Electronic Marking | 1 | Hex | 20 | 14h |
(SA) + 0181h | Revision of Electronic Marking | 1 | Hex | 1 | 01h |
(SA) + 0182h | Fab Lot # | 8 | ASCII | LD87270 | 4Ch, 44h, 38h, 37h, 32h, 37h, 30h, FFh |
(SA) + 018Ah | Wafer # | 1 | Hex | 23 | 17h |
(SA) + 018Bh | Die X Coordinate | 1 | Hex | 10 | 0Ah |
(SA) + 018Ch | Die Y Coordinate | 1 | Hex | 15 | 0Fh |
(SA) + 018Dh | Class Lot # | 7 | ASCII | BR33150 | 42h, 52h, 33h, 33h, 31h, 35h, 30h |
(SA) + 0194h | Reserved for Future | 12 | N/A | N/A | FFh, FFh, FFh, FFh, FFh, FFh, FFh, FFh, FFh, FFh, FFh, FFh |
Fab Lot # + Wafer # + Die X Coordinate + Die Y Coordinate gives a unique ID for each device.
The register maps are copied in this section as a quick reference. See Registers for the full description of the register contents.
Table 73 Status Register 1 (SR1)
Bits | Field name | Function | Type | Default state | Description |
7 | SRWD | Status Register Write Disable | Non-volatile | 0 | 1 = Locks state of SRWD, BP, and configu- ration register bits when WP# is LOW by ignoring WRR command 0 = No protection, even when WP# is LOW |
6 | P_ERR | Programming Error Occurred | Volatile, Read only | 0 | 1 = Error occurred 0 = No error |
5 | E_ERR | Erase Error Occurred | Volatile, Read only | 0 | 1= Error occurred 0 = No error |
4 | BP2 | Block Protection | Volatile if CR1[3] = 1, Non-Volatile if CR1[3] = 0 | 1 if CR1[3] = 1, 0 when shipped from Infineon | Protects selected range of sectors (Block) from Program or Erase |
3 | BP1 | ||||
2 | BP0 | ||||
1 | WEL | Write Enable Latch | Volatile | 0 | 1 = Device accepts Write Registers (WRR), program or erase commands 0 = Device ignores Write Registers (WRR), program or erase commands This bit is not affected by WRR, only WREN and WRDI commands affect this bit. |
0 | WIP | Write in Progress | Volatile, Read only | 0 | 1= Device Busy, a Write Registers (WRR), program, erase or other operation is in progress 0 = Ready Device is in standby mode and can accept commands |
Table 74 Configuration Register (CR1)
Bits | Field name | Function | Type | Default state | Description |
7 | LC1 | Latency Code | Non-Volatile | 0 | Selects number of initial read latency cycles See Latency Code tables (Table 26 through Table 29) |
6 | LC0 | 0 | |||
5 | TBPROT | Configures Start of Block Protection | OTP | 0 | 1 = BP starts at bottom (Low address) 0 = BP starts at top (High address) |
4 | RFU | RFU | OTP | 0 | Reserved for Future Use |
3 | BPNV | Configures BP2-0 in Status Register | OTP | 0 | 1 = Volatile 0 = Non-volatile |
2 | TBPARM | Configures Parameter Sectors location | OTP | 0 | 1 = 4-KB physical sectors at top, (high address) 0 = 4-KB physical sectors at bottom (Low address) RFU in uniform sector devices. |
1 | QUAD | Puts the device into Quad I/O operation | Non-Volatile | 0 | 1 = Quad 0 = Dual or Serial |
0 | FREEZE | Lock current state of BP2-0 bits in Status Register, TBPROT and TBPARM in Configuration Register, and OTP regions | Volatile | 0 | 1 = Block Protection and OTP locked 0 = Block Protection and OTP un-locked |
Table 75 Status Register 2 (SR2)
Bits | Field name | Function | Type | Default state | Description |
7 | RFU | Reserved | 0 | Reserved for Future Use | |
6 | RFU | Reserved | 0 | Reserved for Future Use | |
5 | RFU | Reserved | 0 | Reserved for Future Use | |
4 | RFU | Reserved | 0 | Reserved for Future Use | |
3 | RFU | Reserved | 0 | Reserved for Future Use | |
2 | RFU | Reserved | 0 | Reserved for Future Use | |
1 | ES | Erase Suspend | Volatile, Read only | 0 | 1 = In erase suspend mode. 0 = Not in erase suspend mode. |
0 | PS | Program Suspend | Volatile, Read only | 0 | 1 = In program suspend mode. 0 = Not in program suspend mode. |
Table 76 Bank Address Register (BAR)
Bits | Field name | Function | Type | Default state | Description |
7 | EXTADD | Extended Address Enable | Volatile | 0b | 1 = 4-byte (32 bits) addressing required from command. 0 = 3-byte (24 bits) addressing from command + Bank Address |
6 to 2 | RFU | Reserved | Volatile | 00000b | Reserved for Future Use |
1 | BA25 | Bank Address | Volatile | 0 | RFU for lower density devices |
0 | BA24 | Bank Address | Volatile | 0 | A24 for 256-Mb device, RFU for lower density device |
Table 77 ASP Register (ASPR)
Bits | Field name | Function | Type | Default state | Description |
15 to 9 | RFU | Reserved | OTP | 1 | Reserved for Future Use |
8 | RFU | Reserved | OTP | [59] | Reserved for Future Use |
7 | RFU | Reserved | OTP | Reserved for Future Use | |
6 | RFU | Reserved | OTP | 1 | Reserved for Future Use |
5 | RFU | Reserved | OTP | Reserved for Future Use | |
4 | RFU | Reserved | OTP | Reserved for Future Use | |
3 | RFU | Reserved | OTP | Reserved for Future Use | |
2 | PWDMLB | Password Protection Mode Lock Bit | OTP | 1 | 0 = Password Protection Mode Permanently Enabled. 1 = Password Protection Mode not Permanently Enabled. |
1 | PSTMLB | Persistent Protection Mode Lock Bit | OTP | 1 | 0 = Persistent Protection Mode Permanently Enabled. 1 = Persistent Protection Mode not Permanently Enabled. |
0 | RFU | Reserved | OTP | 1 | Reserved for Future Use |
Note
Default value depends on ordering part number, see Initial delivery state.
Table 78 Password Register (PASS)
Bits | Field name | Function | Type | Default state | Description |
63 to 0 | PWD | Hidden Password | OTP | FFFFFFFF- FFFFFFFFh | Non-volatile OTP storage of 64-bit password. The password is no longer readable after the password protection mode is selected by programming ASP register bit ‘2’ to ‘0’. |
Table 79 PPB Lock Register (PPBL)
Bits | Field name | Function | Type | Default state | Description |
7 to 1 | RFU | Reserved | Volatile | 00h | Reserved for Future Use |
0 | PPBLOCK | Protect PPB Array | Volatile | Persistent Protection Mode = 1 Password Protection Mode = 0 | 0 = PPB array protected until next power cycle or hardware reset 1 = PPB array may be programmed or erased |
Table 80 PPB Access Register (PPBAR)
Bits | Field name | Function | Type | Default state | Description |
7 to 0 | PPB | Read or Program per sector PPB | Non-volatile | FFh | 00h = PPB for the sector addressed by the PPBRD or PPBP command is programmed to ‘0’, protecting that sector from program or erase operations. FFh = PPB for the sector addressed by the PPBRD or PPBP command is erased to ‘1’, not protecting that sector from program or erase operations. |
Table 81 DYB Access Register (DYBAR)
Bits | Field name | Function | Type | Default state | Description |
7 to 0 | DYB | Read or Write per sector DYB | Volatile | FFh | 00h = DYB for the sector addressed by the DYBRD or DYBP command is cleared to ‘0’, protecting that sector from program or erase operations. FFh = DYB for the sector addressed by the DYBRD or DYBP command is set to ‘1’, not protecting that sector from program or erase operations. |
Table 82 Non-Volatile Data Learning Register (NVDLR)
Bits | Field name | Function | Type | Default state | Description |
7 to 0 | NVDLP | Non-Volatile Data Learning Pattern | OTP | 00h | OTP value that may be transferred to the host during DDR read command latency (dummy) cycles to provide a training pattern to help the host more accurately center the data capture point in the received data bits. |
Table 83 Volatile Data Learning Register (NVDLR)
Bits | Field name | Function | Type | Default state | Description |
7 to 0 | VDLP | Volatile Data Learning Pattern | Volatile | Takes the value of NVDLRduring POR or Reset | Volatile copy of the NVDLP used to enable and deliver the Data Learning Pattern (DLP) to the outputs. The VDLP may be changed by the host during system operation. |
Initial delivery state
The device is shipped from Infineon with non-volatile bits set as follows:
The entire memory array is erased: i.e., all bits are set to 1 (each byte contains FFh).
The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased to FFh.
The ID-CFI address space contains the values as defined in the description of the ID-CFI address space.
The Status Register 1 contains 00h (all SR1 bits are cleared to 0’s).
The Configuration Register 1 contains 00h.
The Autoboot register contains 00h.
The Password Register contains FFFFFFFF-FFFFFFFFh.
All PPB bits are ‘1’.
The ASP Register contents depend on the ordering options selected:
Table 84 ASP Register content
Ordering part number model | ASPR default value |
00, 20, 30, R0, A0, B0, C0, D0, 01, 21, 31, R1, A1, B1, C1, D1, 90, Q0, 70, 60, 80, 91, Q1, 71, 61, 81, G0, G1, 40, 41, | FE7Fh |
H0, H1, E0, E1, F0, F1 |
Physical interface
Table 85 Model specific connections[60]
VIO / RFU | Versatile I/O or RFU — Some device models bond this connector to the device I/O power supply, other models bond the device I/O supply to Vcc within the package leaving this package connector unconnected. |
RESET# / RFU | RESET# or RFU — Some device models bond this connector to the device RESET# signal, other models bond the RESET# signal to Vcc within the package leaving this package connector unconnected. |
Note
See Table 2 for signal descriptions.
0.20
C
A-B
0.10 C D
C
2X
0.33
D
A-B
C
0.25 M
0.10 C
0.10 C
SYMBOL | DIMENSIONS | ||
MIN. | NOM. | MAX. | |
A | 2.35 | - | 2.65 |
A1 | 0.10 | - | 0.30 |
A2 | 2.05 | - | 2.55 |
b | 0.31 | - | 0.51 |
b1 | 0.27 | - | 0.48 |
c | 0.20 | - | 0.33 |
c1 | 0.20 | - | 0.30 |
D | 10.30 BSC | ||
E | 10.30 BSC | ||
E1 | 7.50 BSC | ||
e | 1.27 BSC | ||
L | 0.40 | - | 1.27 |
L1 | 1.40 REF | ||
L2 | 0.25 BSC | ||
N | 16 | ||
h | 0.25 | - | 0.75 |
0 | 0° | - | 8° |
0 1 | 5° | - | 15° |
0 2 | 0° | - | - |
NOTES:
ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
0.25 mm FROM THE LEAD TIP.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE LEAD FOOT.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE.
002-15547 *A
Figure 129 S03016 — 16-lead wide plastic small outline package (300-mil body width)
SYMBOL | DIMENSIONS | ||
MIN. | NOM. | MAX. | |
e | 1.27 BSC. | ||
N | 8 | ||
ND | 4 | ||
L | 0.45 | 0.50 | 0.55 |
b | 0.35 | 0.40 | 0.45 |
D2 | 4.70 | 4.80 | 4.90 |
E2 | 4.55 | 4.65 | 4.75 |
D | 6.00 BSC | ||
E | 8.00 BSC | ||
A | 0.70 | 0.75 | 0.80 |
A1 | 0.00 | 0.02 | 0.05 |
A3 | 0.20 REF | ||
K | 0.20 MIN. | ||
NOTES:
DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
ALL DIMENSIONS ARE IN MILLIMETERS.
N IS THE TOTAL NUMBER OF TERMINALS.
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
MAX. PACKAGE WARPAGE IS 0.05mm.
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
10
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT.
002-18827 **
Figure 130 WNG008 — WSON 8-contact (6 8 mm) no-lead package
SYMBOL | DIMENSIONS | |||
MIN. | NOM. | MAX. | ||
A | - | - | 1.20 | |
A1 | 0.20 | - | - | |
D | 8.00 BSC | |||
E | 6.00 BSC | |||
D1 | 4.00 BSC | |||
E1 | 4.00 BSC | |||
MD | 5 | |||
ME | 5 | |||
N | 24 | |||
| 0.35 | 0.40 | 0.45 | |
eE | 1.00 BSC | |||
eD | 1.00 BSC | |||
SD | 0.00 BSC | |||
SE | 0.00 BSC | |||
NOTES:
1.
2.
3.
4.
7
6
5.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS.
BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
002-15534 **
Figure 131 FAB024 — 24-ball BGA (8 6 mm) package
SYMBOL | DIMENSIONS | |||
MIN. | NOM. | MAX. | ||
A | - | - | 1.20 | |
A1 | 0.25 | - | - | |
D | 8.00 BSC | |||
E | 6.00 BSC | |||
D1 | 5.00 BSC | |||
E1 | 3.00 BSC | |||
MD | 6 | |||
ME | 4 | |||
N | 24 | |||
| 0.35 | 0.40 | 0.45 | |
eE | 1.00 BSC | |||
eD | 1.00 BSC | |||
SD | 0.50 BSC | |||
SE | 0.50 BSC | |||
NOTES:
1.
2.
3.
e
4.
5.
6
7
8.
9.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS.
BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
002-15535 *A
Figure 132 FAC024 — 24-ball BGA (6 8 mm) package
The ordering part number is formed by a valid combination of the following:
S25FL 064 S AG M F I 0 0 1
Packing type
0 = Tray
1 = Tube
3 = 13" Tape and reel
Model number (Sector type)
0 = Uniform 64-KB sectors with Hybrid 4-KB sectors
1 = Uniform 256-KB sectors
Model number (Latency type, package details, RESET# and V_IO support)
0 = EHPLC, SO/WSON footprint
2 = EHPLC, 5 × 5 ball BGA footprint
3 = EHPLC, 4 × 6 ball BGA footprint
G = EHPLC, SO footprint with RESET#
R = EHPLC, SO footprint with RESET# and VIO
A = EHPLC, 5 × 5 ball BGA footprint with RESET# and VIO
B = EHPLC, 4 × 6 ball BGA footprint with RESET# and VIO
C = EHPLC, 5 × 5 ball BGA footprint with RESET#
D = EHPLC, 4 × 6 ball BGA footprint with RESET# 9 = HPLC, SO/WSON footprint
4 = HPLC, 5 × 5 ball BGA footprint 8 = HPLC, 4 × 6 ball BGA footprint
H = HPLC, SO footprint with RESET#
Q = HPLC, SO footprint with RESET# and VIO
7 = HPLC, 5 × 5 ball BGA footprint with RESET# and VIO 6 = HPLC, 4 × 6 ball BGA footprint with RESET# and VIO
E = HPLC, 5 × 5 ball BGA footprint with RESET#
F = HPLC, 4 × 6 ball BGA footprint with RESET#
Temperature range/grade
I = Industrial (-40°C to +85°C)
V = Industrial Plus (-40°C to + 105°C)
A = Automotive, AEC-Q100 grade 3 (-40°C to +85°C)
B = Automotive, AEC-Q100 grade 2 (-40°C to +105°C) M = Automotive, AEC-Q100 grade 1 (-40°C to +125°C)
Package material
H = Halogen-free, Lead (Pb)-free F = Halogen-free, Lead (Pb)-free
Package type
M = 16-pin SO package
N = 8-contact WSON 6 x 8 mm package
B = 24-ball BGA 6 x 8 mm package, 1.00 mm pitch
Speed
AG = 133 MHz
DP = 66 MHz DDR DS = 80 MHz DDR
Technology
S = 65-nm MIRRORBIT™ process technology
Density
128 = 128 Mb
256 = 256 Mb
Device family
S25FL 3 V, Serial Peripheral Interface (SPI) flash memory
Notes
EHPLC = Enhanced High Performance Latency Code table.
HPLC = High Performance Latency Code table.
Uniform 64-KB sectors = A hybrid of 32 x 4-KB sectors with all remaining sectors being 64 KB, with a 256B programming buffer.
Uniform 256-KB sectors = All sectors are uniform 256-KB with a 512B programming buffer.
Halogen free definition is in accordance with IEC 61249-2-21 specification.
Valid combinations list configurations planned to be supported in volume for this device. Contact your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Table 86 S25FL128S/S25FL256S valid combinations — Standard
Base ordering part number | Speed option | Package and temperature | Model number | Packing type | Package marking[66] |
S25FL128S or S25FL256S | AG | MFI, MFV | 00, 01, G0, G1, R0, R1 | 0, 1, 3 | FL + (Density) + SA + (Temp) + F + (Model Number) |
NFI, NFV | 00, 01 | 0, 1, 3 | FL + (Density) + SA + (Temp) + F + (Model Number) | ||
BHI, BHV | 20, 21, 30, 31, A0, A1, B0, B1, C0, C1, D0, D1 | 0, 3 | FL + (Density) + SA + (Temp) + H + (Model Number) | ||
DP | MFI | G0, G1 | 0, 1, 3 | FL + (Density) + SD + (Temp) + F + (Model Number) | |
MFV | 00, 01 | 0, 1, 3 | |||
NFI, NFV | 00 | 0, 1, 3 | FL + (Density) + SD + (Temp) + F + (Model Number) | ||
BHI, BHV | 21, C0, C1, D1 | 0, 3 | FL + (Density) + SD + (Temp) + H + (Model Number) | ||
DS | MFI, MFV | 00, 01, G0, G1, R0, R1 | 0, 1, 3 | FL + (Density) + SS + (Temp) + F + (Model Number) | |
NFI, NFV | 00, 01 | 0, 1, 3 | FL + (Density) + SS + (Temp) + F + (Model Number) | ||
BHI, BHV | 20, 21, 30, 31, A0, A1, B0, B1, C0, C1, D0, D1 | 0, 3 | FL + (Density) + SS + (Temp) + H + (Model Number) |
Notes
Example, S25FL256SAGMFI000 package marking would be FL256SAIF00.
Contact the factory for additional Extended (-40°C to + 125°C) temperature range OPN offerings.
The table below lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The table will be updated as new combinations are released. Contact your local sales repre- sentative to confirm availability of specific combinations and to check on newly released combinations.
Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949 compliance.
Table 87 S25FL128S, S25FL256S valid combinations — Automotive grade / AEC-Q100
Base ordering part number | Speed option | Package and temperature | Model number | Packing type | Package marking |
S25FL128S or S25FL256S | AG | MFA, MFB, MFM | 00, 01, G0, G1, R0, R1 | 0, 1, 3 | FL + (Density) + SA + (Temp) + F + (Model Number) |
NFA, NFB, NFM | 00, 01 | 0, 1, 3 | FL + (Density) + SA + (Temp) + F + (Model Number) | ||
BHA, BHB, BHM | 20, 21, 30, 31, A0, A1, B0, B1, C0, C1, D0, D1 | 0, 3 | FL + (Density) + SA + (Temp) + H + (Model Number) | ||
DP | NFB | 00 | 0, 1, 3 | FL + (Density) + SD + (Temp) + F + (Model Number) | |
BHB | 21, C0 | 0, 3 | FL + (Density) + SD + (Temp) + H + (Model Number) | ||
MFB | 01 | 0, 1, 3 | FL + (Density) + SD + (Temp) + F + (Model Number) | ||
DS | MFA, MFB, MFM | 00, 01, G0, G1, R0, R1 | 0, 1, 3 | FL + (Density) + SS + (Temp) + F + (Model Number) | |
NFA, NFB, NFM | 00, 01 | 0, 1, 3 | FL + (Density) + SS + (Temp) + F + (Model Number) | ||
BHA, BHB, BHM | 20, 21, 30, 31, A0, A1, B0, B1, C0, C1, D0, D1 | 0, 3 | FL + (Density) + SS + (Temp) + H + (Model Number) |
Table 88 Acronyms used in this document
Acronym | Description |
Command | All information transferred between the host system and memory during one period while CS# is LOW. This includes the instruction (sometimes called an operation code or opcode) and any required address, mode bits, latency cycles, or data. |
DDP (Dual die package) | Two die stacked within the same package to increase the memory capacity of a single package. Often also referred to as a multi-chip package (MCP). |
DDR (Double data rate) | When input and output are latched on every edge of SCK. |
ECC | ECC unit = 16-byte aligned and length data groups in the main flash array and OTP array, each of which has its own hidden ECC syndrome to enable error correction on each group. |
Flash | The name for a type of EEPROM that erases large blocks of memory bits in parallel, making the erase operation much faster than early EEPROM. |
High | A signal voltage level ≥ VIH or a logic level representing a binary one (‘1’). |
Instruction | The 8-bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). The instruction is always the first 8-bits trans- ferred from host system to the memory in any command. |
Low | A signal voltage level VIL or a logic level representing a binary zero (‘0’). |
LSb (Least significant bit) | The right most bit, with the lowest order of magnitude value, within a group of bits of a register or data value. |
MSb (Most significant bit) | The left most bit, with the highest order of magnitude value, within a group of bits of a register or data value. |
LSB (Least significant byte) | The right most byte, within a group of bytes. |
MSB (Most significant byte) | The left most bit, within a group of bytes |
Non-volatile | No power is needed to maintain data stored in the memory. |
OPN (Ordering part number) | The alphanumeric string specifying the memory device type, density, package, factory non-volatile configuration, etc., used to select the desired device. |
Page | 512-bytes or 256-bytes aligned and length group of data. The size assigned for a page depends on the ordering part number. |
PCB | printed circuit board |
PPAP | production part approval process |
Register bit references | Are in the format: Register_name[bit_number] or Register_name[bit_range_MSb: bit_range_LSB] |
SDR (Single data rate) | When input is latched on the rising edge and output on the falling edge of SCK. |
Table 88 Acronyms used in this document (continued)
Acronym | Description |
Sector | Erase unit size; depending on device model and sector location this may be 4 KB, 64 KB or 256 KB. |
Write | An operation that changes data within volatile or non-volatile registers bits or non-volatile flash memory. When changing non-volatile data, an erase and repro- gramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile data is modified – as a single operation. The non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data. |
Document revision | Date | Description of changes |
** | 2011-05-25 | Initial release |
*A | 2011-11-18 | Global: Promoted datasheet to Preliminary status Corrected minor typos and grammatical errors Performance Summary: Updated the Serial Read 50 MHz current consumption value from 14 mA (max) to 16 mA (max) Updated the Serial Read 133 MHz current consumption value from 25 mA (max) to 33 mA (max) Power-Up and Power-DownRemoved the statement “The device draws ICC1 (50 MHz value) during tPU” DC Characteristics: Updated the ICC1 Active Power Supply Current (READ) Serial SDR @ 50 MHz maximum value from 14 mA to 16 mA Updated the ICC1 Active Power Supply Current (READ) Serial SDR @ 133 MHz maximum value from 25 mA to 33 mA SDR AC Characteristics: Added the tCSH CS# Active Hold Time (Relative to SCK) maximum value of 3000 ns, with a note indicating that this only applies during the Program/Erase Suspend/Resume commands DDR AC Characteristics: Added the tCSH CS# Active Hold Time (Relative to SCK) maximum value of 3000 ns, with a note indicating that this only applies during the Program/Erase Suspend/Resume commands Capacitance Characteristics: Added a Note 1, pointing users to the IBIS models for more details on capacitance Physical Interface: Corrected pin 5 of the SOIC 16 Connection Diagram from NC to DNU Corrected pin 13 of the SOIC 16 Connection Dig ram from DNU to NC Replaced the WNF008 drawing with the WNG008 drawing Updated the FAB024 drawing to the latest version ASP Register: Corrected the statement “The programming time of the ASP Register is the same as the typical byte programming time” to “The programming time of the ASP Register is the same as the typical page programming time” Persistent Protection Bits: Corrected the statement “Programming a PPB bit requires the typical byte programming time” to “Programming a PPB bit requires the typical page programming time” Register Read or Write: Corrected the statement “…the device remains busy and unable to receive most new operation commands.” to “..the device remains busy. Under this condition, only the CLSR, WRDI, RDSR1, RDSR2, and software RESET commands are valid commands.” |
Document revision | Date | Description of changes |
*A (Cont) | 2011-11-18 | Page Program (PP 02h or 4PP 12h): Removed the statement “If more than a page of data is sent to the device, previ- ously latched data are discarded and the last page worth of data (either 256 or 512 bytes) are programmed in the page. This is the result of the device being equipped with a page program buffer that is only page size in length.” Embedded Algorithm Performance Tables: Updated the t_W WRR Write Time typical value from 100 ms to 140 ms and the maximum value from 200 ms to 500 ms Updated t_PP Page Programming Time (256 bytes) maximum value from 550 µs to 750 µs. Added Note 3 and Note 4 to Table 10.7 to note shared performance values across other commands Updated the t_ESL Erase Suspend Latency maximum value from 40 µs to 45 µs. Device ID and Common Flash Interface (ID-CFI) Address Map: CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC DDR table: corrected the data of offset 01h from 32h to 2Ah Ordering Information: Added E0, E1, F0, F1, G0, and G1 as valid model numbers Broke out the 2 character length model number decoder into separate characters to clarify format and save space Corrected the valid S25FLxxxSAGMFI model numbers from R0 and R1 to G0 and G1 Updated the Package Marking format to help identify speed differences across similar devices Added G0 and G1 as valid model number combinations for SDR SOIC OPNs Removed 20, 21, 30, and 31 as valid model numbers combinations for DDR BGA OPNs |
*B | 2012-03-22 | DC Characteristics: Updated ICC1 values, added note AC Characteristics: AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V) table: Moved tSU value to tCSH, added note AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V) table: Moved tSU value to tCSH, added note AC Characteristics 66 MHz Operation table: added note Command Set Summary: S25FL128S and S25FL256S Command Set (sorted by function) table: added note Device ID and Common Flash Interface (ID-CFI) Address Map: Updated CFI Alternate Vendor-Specific Extended Query Parameter 0 table Updated CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands table Updated CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset Timing table Ordering Information: Valid Combinations table: added BHV to Package and Temperature for Models C0, Do and C1, D1 |
Document revision | Date | Description of changes |
*C | 2012-06-13 | SDR AC Characteristics: Updated tHO value from 0 Min to 2 ns Min |
*D | 2012-07-12 | Global: Promoted datasheet designation from Preliminary to Full Production |
*E | 2013-12-20 | Global: 80 MHz DDR Read operation added Performance Summary: Updated Maximum Read Rates DDR (VIO = VCC = 3V to 3.6V) table. Current Consumption table: added Quad DDR Read 80 MHz. Migration Notes: FL Generations Comparison table: updated DDR values for FL-S SDR AC Characteristics: Updated Clock Timing figure DDR AC Characteristics: Updated AC Characteristics — DDR Operation table DDR Output Timing: Updated SPI DDR Data Valid Window figure and Notes Ordering Information: Added 80 MHz to Speed option. Valid Combinations table: added DS Speed Option. |
*F | 2014-03-17 | SDR AC Characteristics: AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V) table: removed tV min AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V) table: removed tV min Ordering Information: Fix typo: Add DDR for 80 MHz for the DS Speed option. Valid Combinations table: Addition of more OPNs. |
*G | 2014-10-10 | Global: Added Extended Temperature Range: -40°C to 125°C SDR AC Characteristics: AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V) table: corrected tSU Min Configuration Register 1 (CR1): Latency Codes for DDR Enhanced High Performance table: added 80 MHz DDR Fast Read (DDRFR 0Dh, 4DDRFR 0Eh): Updated figures: Continuous DDR Fast Read Subsequent Access (3-byte Address [ExtAdd=0, EHPLC=11b]) Continuous DDR Fast Read Subsequent Access (4-byte Address [ExtAdd=1], EHPLC=01b) |
Document revision | Date | Description of changes |
*G (Cont) | 2014-10-10 | Initial Delivery State: ASP Register Content table: removed ASPR Default Value row FE4Fh Ordering Information FL128S and FL256S: Added Extended Temperature Range: -40°C to 125°C Updated Valid Combinations table |
*H | 2015-05-09 | Global: Updated description of DDR commands to reflect maximum operating clock frequency of 80 MHz (from 66 MHz) Command Set Summary: S25FL128S and S25FL256S Command Set (sorted by function) table: changed max DDR frequency from 66 MHz to 80 MHz for all applicable DDR commands Software Interface Reference: S25FL128S and S25FL256S Instruction Set (sorted by instruction) table: changed max DDR frequency from 66 MHz to 80 MHz for all applicable DDR commands Valid Combinations: Corrected the Package Marking for DS Speed Option |
*I | 2015-08-24 | Replaced “Automotive Temperature Range” with “Industrial Plus Temperature Range” in all instances across the document. Updated Pinouts and signal descriptions: Updated Versatile I/O Power Supply (VIO): Updated description. Updated to Cypress template. |
*J | 2016-09-22 | Added ECC related information in all instances across the document. Added Automotive Temperature Range related information in all instances across the document. Added Logic block diagram. Updated Electrical specifications: Added Thermal resistance. Updated Operating ranges: Updated Table 7: Updated minimum value of VCC (low) parameter. Changed minimum value of tPD parameter from 1.0 µs to 15.0 µs. Updated Timing specifications: Updated SDR AC characteristics: Updated Table 13: Removed Note “For Industrial Plus (-40°C to +105°C) and Extended (-40°C to +125°C) temperature range, all SCK clock frequencies are 5% slower than the Max values shown.” and its references. Updated Table 14: Removed Note “For Industrial Plus (-40°C to +105°C) and Extended (-40°C to +125°C) temperature range, all SCK clock frequencies are 5% slower than the Max values shown.” and its references. Updated DDR AC characteristics: Updated Table 15: Removed Note “For Industrial Plus (-40°C to +105°C) and Extended (-40°C to +125°C) temperature range, all SCK clock frequencies are 5% slower than the Max values shown.” and its references. Changed minimum value of tHO parameter corresponding to 66 MHz from 0 ns to 1.5 ns. |
Document revision | Date | Description of changes |
*J (Cont) | 2016-09-22 | Updated Address space maps: Updated Registers: Added ECC Status Register (ECCSR). Updated Commands: Updated Command set summary: Updated Extended addressing: Updated Table 48: Removed Note “For Industrial Plus (-40°C to +105°C) and Extended (-40°C to +125°C) temperature range, all Maximum Frequency values are 5% slower than the Max values shown.” and its references. Updated Register access commands: Updated Write Registers (WRR 01h): Updated description. Added ECC Status Register Read (ECCRD 18h). Updated Program flash array commands: Updated Program granularity: Added Automatic ECC. Added Data integrity. Updated Device identification: Added Device ID and common flash interface (ID-CFI) ASO map — Automotive only. Updated Ordering information: Added Automotive Temperature Range related information in valid combina- tions. Updated Valid combinations — Standard: Updated Table 86: Updated entire table. Added Valid combinations — Automotive grade / AEC-Q100. Updated to new template. |
*K | 2017-03-16 | Updated Table 8. Added Table 9. Updated Figure 130. Updated Figure 131. Updated Figure 132. Updated tSU in Table 13. |
*L | 2017-04-27 | Updated Quad Page Program (QPP 32h or 38h, or 4QPP 34h). Updated Sales page. Updated Cypress logo. |
*M | 2017-05-23 | Added Model Number “21” in Table 87. |
*N | 2017-06-14 | Updated Ordering information. Added part number (S25FL128SDPMFB010) in Table 87. |
*O | 2018-03-15 | Table 13 and Table 14: Removed the Max value of tCSH and updated the Max value of tSU as “3000”. |
Document revision | Date | Description of changes |
*P | 2018-08-07 | Updated Acronyms: Replaced MSB with MSb and LSB with LSb. Added DDR data valid timing using DLP. Updated Ordering information: Added note 6. Updated Table 84: Added Model # G0, G1, 40, 41, H0, H1, E0, E1, F0, F1. Updated Table 25: Updated CR1[4] from RFU to DNU. Updated the following figures: Figure 9, Figure 35, Figure 36, Figure 39, Figure 40, Figure 131, Figure 43, Figure 46 through Figure 50, Figure 54 through Figure 65, and Figure 93 through Figure 121. |
*Q | 2019-04-30 | Updated Section 5.2 Thermal resistance on page 31. Updated Copyright information. |
*R | 2022-06-10 | Updated Chip Select (CS#). Updated Ordering information. Updated Thermal resistance. Updated Table 8 and Table 9. Updated table footnote 50. Updated to Infineon template. |
*S | 2022-08-10 | Corrected Ordering part number. Updated Figure 132: Spec 002-15535 ** to *A. |
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